Patents by Inventor Chung-Hui Chen

Chung-Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY
    Publication number: 20160172442
    Abstract: In some embodiments, a semiconductor structure includes first and second GAA structures configured to form corresponding similar first and second circuits. At least one of the first or second GAA structure includes at least one GAA device. A GAA device of the at least one GAA device includes at least one nanowire and a gate region. A nanowire of the at least one nanowire has a cross-section asymmetrical with respect to a middle line of the cross-section. The cross-section has first and second end lines substantially parallel the middle line. The first end line is shorter than the second end line. The gate region wraps all around part of the nanowire. The first and second GAA structures have substantially a same of a number of GAA devices in the at least one GAA device configured to have current flow from the first end line to the second end line.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Inventor: CHUNG-HUI CHEN
  • Temperature/voltage detection circuit
    Patent number: 9354124
    Abstract: A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: May 31, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Chung-Hui Chen
  • FinFET with embedded MOS varactor and method of making same
    Patent number: 9343552
    Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Jaw-Juinn Horng, Po-Zeng Kang
  • Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
    Patent number: 9305864
    Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn Horng, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
  • Generating a semiconductor component layout
    Patent number: 9305135
    Abstract: A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Chen, Yung-Chow Peng, Chung-Hui Chen, Chih Ming Yang
  • Semiconductor mismatch reduction
    Patent number: 9287252
    Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hui Chen, Ruey-Bin Sheen, Yung-Chow Peng, Po-Zeng Kang, Chung-Peng Hsieh
  • Circuits using gate-all-around technology
    Patent number: 9281363
    Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Hui Chen
  • GENERATING A SEMICONDUCTOR COMPONENT LAYOUT
    Publication number: 20150356235
    Abstract: A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations.
    Type: Application
    Filed: August 19, 2015
    Publication date: December 10, 2015
    Inventors: Chien-Hung CHEN, Yung-Chow PENG, Chung-Hui CHEN, Chih-Ming YANG
  • FinFET structure with novel edge fins
    Patent number: 9196540
    Abstract: A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • CONDUCTIVE LINES IN CIRCUITS
    Publication number: 20150332960
    Abstract: In a method, conductive lines used in a circuit are formed. Signal traces of a plurality of signal traces are grouped to a first group of first signal traces or a second group of second signal traces. A first mask is used to form a first conductive line for a first signal trace of the first group. A second mask is used to form a second conductive line for a second signal trace of the second group. The first traces each have a first width. The second traces each have a second width different from the first width. The grouping is based on at least one of following conditions: a current flowing through a signal trace of the signal traces of the plurality of signal traces, a length of the signal trace, a resistivity of the signal trace, or a resistivity-capacitive constant of the signal trace.
    Type: Application
    Filed: May 12, 2015
    Publication date: November 19, 2015
    Inventor: Chung-Hui CHEN
  • DECOUPLING CAPACITOR AND METHOD OF MAKING SAME
    Publication number: 20150333054
    Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui CHEN
  • CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY
    Publication number: 20150303259
    Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 22, 2015
    Inventor: CHUNG-HUI CHEN
  • Device layout for reference and sensor circuits
    Patent number: 9166067
    Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn Horng, Chung-Hui Chen, Sun-Jay Chang, Chia-Hsin Hu
  • FinFET with Embedded MOS Varactor and Method of Making Same
    Publication number: 20150270368
    Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.
    Type: Application
    Filed: May 21, 2015
    Publication date: September 24, 2015
    Inventors: Wan-Te Chen, Chung-Hui Chen, Jaw-Juinn Horng, Po-Zeng Kang
  • Generating a semiconductor component layout
    Patent number: 9141754
    Abstract: A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Chen, Yung-Chow Peng, Chung-Hui Chen, Chih-Ming Yang
  • Decoupling capacitor and method of making same
    Patent number: 9123556
    Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui Chen
  • Guard structure for semiconductor structure and method of forming guard layout pattern for semiconductor layout pattern
    Patent number: 9093494
    Abstract: A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jaw-Juinn Horng, Jen-Hao Yeh, Fu-Chih Yang, Chung-Hui Chen
  • SEMICONDUCTOR DEVICE WITH SELF-HEAT REDUCING LAYERS
    Publication number: 20150200249
    Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Amit KUNDU, Jaw-Juinn HORNG, Chung-Hui CHEN
  • Integrated circuits with reduced voltage across gate dielectric and operating methods thereof
    Patent number: 9076858
    Abstract: An integrated circuit includes a first pad configured to carry a signal, a first receiver having an input node, a second receiver having an input node, a first pass gate, and a second pass gate. The first pass gate is coupled between the first pad and the input node of the first receiver. The first pass gate is configured to be turned on when the signal on the first pad is greater than a first voltage level. The second pass gate is coupled between the first pad and the input node of the second receiver. The second pass gate is configured to be turned on when the signal on the first pad is less than a second voltage level.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: July 7, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • FinFET with embedded MOS varactor and method of making same
    Patent number: 9064725
    Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Jaw-Juinn Horng, Po-Zeng Kang