Abstract: In a method for manufacturing a semiconductor device, a cell well, a logic well and a high voltage well are formed in a first, a second and a third regions of a substrate. A first and a second stacked structures are formed on the first and second regions. A first and a second word line wells are formed in the cell well. First spacers are formed on sidewalls of the first and second stacked structures. A first gate oxide layer is formed on the third region and the first and second word line wells. A portion of the first stacked structure is removed to form a first and a second device structures. A second gate oxide layer is formed to cover the first, second and third regions. A first and a second word lines are formed adjacent to the first and second device structures.

Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.

Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.

Abstract: A storage device includes a semiconductor substrate, a control gate, a word line, a dielectric layer, a charge storage nitride layer, and a blocking layer. The semiconductor substrate has a source region and a drain region. The control gate and a word line are disposed over the semiconductor substrate and located between the source and drain regions. The dielectric layer is in contact with the semiconductor substrate and disposed between the semiconductor substrate, the control gate, and the word line. The charge storage nitride layer is disposed between the dielectric layer and the control gate. The blocking layer is disposed between the charge storage nitride layer and the control gate.

Abstract: A semiconductor device includes a substrate, a trap storage structure, a control gate, a cap structure, a word line well, a source line, spacers, a gap oxide layer, a word line and a gate oxide layer. The trap storage structure includes a first oxide layer, a nitride layer and a second oxide layer stacked on the substrate. The control gate is directly on the trap storage structure. The cap structure is stacked on the control gate to form a stacked structure. The word line well and the source line are disposed in the substrate at opposite sides of the stacked structure. The spacers are on sidewalls of the stacked structure. The gap oxide layer is on a sidewall of one spacer. The word line is on the word line well and the gap oxide layer. The gate oxide layer is between the word line and the word line well.

Abstract: A memory device and an operation method thereof are provided. The memory device includes a semiconductor substrate and an oxide-nitride-oxide (ONO) gate structure located on the semiconductor substrate. The ONO gate structure includes a bottom oxide layer, a top oxide layer and a nitride layer. The nitride layer is located between the bottom oxide layer and the top oxide layer. The bottom oxide layer is located closer to the semiconductor substrate than the top oxide layer. The bottom oxide layer has a first thickness, and the top oxide layer has a second thickness smaller the first thickness. The operation method includes an erasing operation and a programming operation. Electrons are attracted into the ONO gate structure through the bottom oxide layer in the programming operation. Electrons trapped in the ONO gate structure escape from the ONO gate structure through the top oxide layer.

Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.

Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.

Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.

Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Abstract: A method for collocating a clothing accessory on a human body for an electronic apparatus, is provided. A human body picture is shown on a display unit, and a human body description file corresponding to a human body model included in the human body picture is obtained from a database. A clothing accessory picture is obtained from another database based on a user choice, and a clothing accessory description file corresponding to a clothing accessory model included in the clothing accessory picture. The object picture is superposed on the human body picture automatically according to the human body and the object description files.

Abstract: A method for collocating a clothing accessory on a human body for an electronic apparatus, is provided. A human body picture is shown on a display unit, and a human body description file corresponding to a human body model included in the human body picture is obtained from a database. A clothing accessory picture is obtained from another database based on a user choice, and a clothing accessory description file corresponding to a clothing accessory model included in the clothing accessory picture. The object picture is superposed on the human body picture automatically according to the human body and the object description files.

Abstract: Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells.

Abstract: Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells.

Abstract: A dance game system includes a host and a motion sensor. The host includes a prompting unit using indicators to prompt dance step directions. The motion sensor includes an acceleration sensor sensing user's dance step directions and communicating with the host wirelessly. The dance game system can operate without using a display unit (such as TV) or dance pads. Therefore, the dance game system is safer and easy to carry about, and the operation thereof is not limited by dance pads.

Abstract: The present invention relates to a linear micro motor having an forward and backward reciprocating motion. The linear micro motor includes at least two actuators which can be a scratch drive actuator (SDA), a bounce drive actuator (BDA) or a combination thereof. To achieve the reciprocating motion, the linear micro motor is arranged in a way that at least two SDAs are disposed in an opposite manner, at least two BDAs are disposed in an opposite manner, or at least a SDA and at least a BDA are disposed in an identical manner. The linear micro motor of the present invention in accordance with the arrangement of the actuators can be realized to be applicable to a digital camera or camera phone by the advancing and receding linear motion caused by the motion of the actuators to achieve a focus-adjustable liquid crystal lens.

Abstract: A digital picture frame system includes a storage unit, a display unit, a control unit, a first port, a first user interface and a power supply unit. The control unit is electrically connected with the storage unit and the display unit to access the storage unit and deliver a picture to the display unit to display. The first port electrically connected to the control unit is used for electrically connecting to an external electronic device. The first user interface electrically connected to the control unit is used for sensing motion of the digital picture frame system or voice to operate the digital picture frame system. The power supply unit electrically connected to the control unit is used for providing a power required for the operation of the digital picture frame system. The above-mentioned digital picture frame system is operated by shaking or voice activation, in a preferred embodiment, further can process picture with special efficacy, therefore there are increased interaction and interest.

Abstract: The present invention relates to a linear micro motor having an forward and backward reciprocating motion. The linear micro motor includes at least two actuators which can be a scratch drive actuator (SDA), a bounce drive actuator (BDA) or a combination thereof. To achieve the reciprocating motion, the linear micro motor is arranged in a way that at least two SDAs are disposed in an opposite manner, at least two BDAs are disposed in an opposite manner, or at least a SDA and at least a BDA are disposed in an identical manner. The linear micro motor of the present invention in accordance with the arrangement of the actuators can be realized to be applicable to a digital camera or camera phone by the advancing and receding linear motion caused by the motion of the actuators to achieve a focus-adjustable liquid crystal lens.

Abstract: A pretend play toy with virtual reality interaction is disclosed. Children play toys on a platform in pretend play, and a circuit board underneath unseen by the children can sensor toys' characters and positions for playing virtual scene on the display where the children have interaction with the virtual playground. The present invention combines the physical toys and children's imagination on the display like TV, and let the children unconsciously learn and enhance their creativity and imagination.