Abstract: A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer.

Abstract: A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.

Abstract: An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: Method for the production of a building material, in particular mortar or concrete from an alkali activated hydraulic binder, in which at least one dispersing agent and at least one set modifier is added to the mix, in which at least the dispersing agent is added after mixing the binder with water.

Abstract: Provided is a silver nanowire-containing composition for a biosensor strip, a biosensor strip comprising the same and its preparation method. The biosensor strip comprises a conductive pattern layer made of the silver nanowire-containing composition. With the aspect ratio of 50 to 500, the silver nanowire-containing composition has good dispersion and high conductivity, such that the biosensor strip comprising the same can have high stability and provide a more accurate and efficient detection.

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region. The first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.

Abstract: A method for the production of an alkali activated hydraulic binder, with the binder comprising slag, natural aluminum silicates, and an alkali activator, and the binder being free of CaSO4. The slag is provided in amounts greater than or equal to 20% (w/w), and the natural aluminum silicates are different from furnace slag, and are provided in amounts from 5 to 75% (w/w). The alkali activator is provided in an amount which corresponds to a Na2O equivalent defined as (Na2O+0.658 K2O) (ASTM C 150) between 0.7 and 4% (w/w). The method includes the step of heat treating a mixture of the slag, the natural aluminium silicates, and the alkali activator at temperatures between 40° C. and 50° C. for 4 to 6 hours.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: An optical substrate having a structured surface that enhances brightness and reduces moire effect. The optical substrate has a three-dimensionally varying, structured light output surface that comprises an irregular prismatic structure. The irregular prismatic structure may be viewed as comprising longitudinal prism blocks or rows thereof, arranged laterally defining peaks and valleys. Adjacent peaks, adjacent valleys, and/or adjacent peak and valley may be parallel or non-parallel, in an orderly, semi-orderly, random, or quasi-random manner. The lateral adjacent peaks, adjacent valleys, and/or adjacent peak and valley are not parallel. The adjacent irregular prism blocks may be irregular longitudinal sections having the same length, or random or quasi-random irregular sections having different lengths. The facets of each prism block may be flat, or curved (convexly and/or concavely).

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: A casing of a turbocharger has a main body and a heat dissipating layer disposed on an outer surface of the main body. When heat inside the main body is conducted to the outer surface of the main body, the heat dissipating layer dissipates the heat quickly. Since the heat does not accumulate in the main body, temperature of the main body is low and the casing does not oxidize under high temperature. Therefore, the casing of the turbocharger has low manufacturing cost and is economical.

Abstract: An optical substrate having a structured surface that enhances brightness and reduces moiré effect. The optical substrate has a three-dimensionally varying, structured light output surface that comprises an irregular prismatic structure. The irregular prismatic structure may be viewed as comprising longitudinal prism blocks or rows thereof, arranged laterally defining peaks and valleys. Adjacent peaks, adjacent valleys, and/or adjacent peak and valley may be parallel or non-parallel, in an orderly, semi-orderly, random, or quasi-random manner. The lateral adjacent peaks, adjacent valleys, and/or adjacent peak and valley are not parallel. The adjacent irregular prism blocks may be irregular longitudinal sections having the same length, or random or quasi-random irregular sections having different lengths. The facets of each prism block may be flat, or curved (convexly and/or concavely).

Abstract: An optical substrate possesses a structured surface that enhances luminance or brightness and reduces the effects of structural defects on perceived image quality. User perceivable image cosmetic defects caused by manufacturing or handling, can be masked by introducing structural irregularities in the optical substrate, which may be non-facet flat sections or in-kind to the defects. Optical defects caused by non-facet flat sections in the prism structure of the optical substrate (e.g., flat-bottom valleys with a certain valley bottom thickness above the base layer, and/or flat-top peaks, and/or openings in the optical substrates that expose flat sections of underlying base layer) can be masked by providing distributed in-kind non-facet flat sections (e.g., flat-bottom valleys, and/or flat-top peaks, and/or openings exposing sections of underlying base layer), to diffuse the prominence of the original defects with the introduced irregularities.

Abstract: A semiconductor integrated circuit device including: a diffusion area defined by an isolation region in a substrate; a PMOS transistor comprising a metal gate and a high-k dielectric over the diffusion area and source/drain regions sandwiching the metal gate in a first direction; a plurality of dummy diffusion areas surrounding and spaced apart from the diffusion area; and a plurality of first dummy patterns at the two sides of the PMOS transistor in a second direction perpendicular to the first direction and between the dummy diffusion areas and the diffusion area.

Abstract: A method and apparatus for improving yield ratio of testing are disclosed. The method includes the following steps. First of all, devices are tested and electromagnetic interference is measured. Next, the test results are examined for whether the devices pass the test or not. Then, electromagnetic interference data are examined for whether the electromagnetic interference data are over a predetermined standard if the devices fail the test. The above-mentioned steps are performed again if the electromagnetic interference data are over a predetermined standard. The test is terminated if the devices still fail the test and the values of electromagnetic interference are still over a predetermined standard.

Abstract: A method for the production of an alkali activated hydraulic binder, with the binder comprising slag, natural aluminum silicates, and an alkali activator, and the binder being free of CaSO4. The slag is provided in amounts greater than or equal to 20% (w/w), and the natural aluminum silicates are different from furnace slag, and are provided in amounts from 5 to 75% (w/w). The alkali activator is provided in an amount which corresponds to a Na2O equivalent defined as (Na2O+0.658K2O) (ASTM C 150) between 0.7 and 4% (w/w). The method includes the step of heat treating a mixture of the slag, the natural aluminium silicates, and the alkali activator at temperatures between 40° C. and 50° C. for 4 to 6 hours.

Abstract: Soft gel capsules are formed from an outer gelatin-containing shell and a filling. The filling includes a probiotic and a dessicant.