Abstract: Proposed is a stick type cosmetic container that includes a first holder for supporting the underside of a cosmetic material to allow the cosmetic material to move in upward and downward directions, a handle for controlling the upward and downward movements of the cosmetic material and having a first hollow portion formed at the inside thereof, an inner container located at the first hollow portion and thus rotatable with respect to the handle and having fixing and fastening grooves formed on the lower end periphery thereof and thus fixedly fastened to the handle whenever the inner container rotates once, and a second holder located inside the inner container to support the underside of the first holder.

Abstract: The purpose of the present invention is to provide: a crosslinked hyaluronic acid hydrogel in which a crosslinking agent and a polyol are used to reduce toxicity during crosslinking, and thereby enhance safety while increasing persistence in the body; and a filler composition including the crosslinked hyaluronic acid hydrogel.

Abstract: A headphone includes a headgear and two earmuffs connected to opposite ends of the headgear, and each of the earmuffs includes an adjustment assembly. The adjustment assembly includes a base, two elastic members, two protrusions, and two sliding blocks. The base has two opposite accommodating parts and two guiding grooves. The elastic members are disposed in the accommodating parts, respectively, and the elastic members extend along a first axial direction. The protrusions are slidably connected to the guiding grooves, respectively, and protrude into the accommodating parts. The sliding blocks are disposed in the accommodating parts, respectively, and each of the sliding blocks is respectively connected between the corresponding protrusion and the corresponding elastic member.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: Antibody-mediated rejection (ABMR) is one of the main obstacles to successful transplantation, including ABO blood group-incompatible (ABOi) transplantation. C4d deposition is a marker of ABMR and is also found in most ABOi allograft tissues. Described herein are anti-C4d CAR Tregs that suppress ABMR in ABOi allografts. Anti-C4d CAR Tregs prepared by retroviral transduction of CAR into CD62L +CD4 +CD25 +Tregs, expressed Foxp3, CD25, CTLA-4, LAP, and GITR to similar extents as non-transduced Tregs. Anti-C4d CAR Tregs were activated by specific binding to C4d and suppressed in vitro T cell proliferation as well as non-transduced Tregs. Furthermore, adoptive transfer of anti-C4d CAR Tregs significantly prolonged mouse ABOi heart allograft survival (P<0.05).

Abstract: A UE for beam failure detection is provided. The UE includes a radio frequency (RF) signal processing device. The RF signal processing device receives a first candidate-beam reference-signal (RS) list and a second candidate-beam RS list and reports a beam failure information. The first candidate-beam RS list is associated with a first beam-failure-detection RS (BFD-RS) set and the second candidate-beam RS list is associated with a second BFD-RS set. The beam failure information includes at least one of following: at least on component carrier (CC) index, at least one new candidate beam, an identity of BFD-RS set, or an CORESETPoolIndex.

Abstract: A multilayer electronic component includes: a body including dielectric layers and having first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; side margin portions disposed on the fifth and sixth surfaces, respectively; and external electrodes disposed on the third and fourth surfaces, respectively. The body includes an active portion including internal electrodes disposed alternately with the dielectric layers in the first direction, one of the internal electrodes includes a central portion and an interface portion disposed between the central portion and one of the dielectric layers, and the interface portion and one of the side margin portions include Sn.

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

Abstract: The present application relates to a hybrid cord including a bio-based nylon primarily twisted yarn. According to the present application, while including a primarily twisted yarn including bio-based nylon having a higher modulus compared to chemical-based nylon, there is provided a hybrid cord and has elongation and fatigue resistance equivalent to or higher than commercially required levels (i.e., the level that the cord including a conventional chemical-based nylon primarily twisted yarn has).

Abstract: Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.

Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.

Abstract: A multilayer ceramic capacitor includes a ceramic body having a dielectric layer, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion arranged on end portions of the internal electrodes exposed through respective opposing surfaces of the ceramic body. The ceramic body includes an active portion having the plurality of internal electrodes arranged to overlap each other with the dielectric layer interposed therebetween to form capacitance, and cover portions disposed above an uppermost and below a lowermost internal electrode of the active portion. The first and second side margin portions include tin (Sn), and a content of Sn included in the first and second side margin portions is greater than a content of Sn included in the dielectric layer of the active portion.

Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion respectively arranged on end portions of the internal electrodes exposed to first and second surfaces. The first and second side margin portions each include a first region adjacent to an outward facing side surface of the respective side margin portion, and a second region adjacent to the internal electrodes exposed to the first and second surfaces of the ceramic body, and an average size of dielectric grains included in the second region is larger than an average size of dielectric grains included in the first region.

Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Abstract: An optical fingerprint sensing module includes an image sensing device, a light source and a light shielding structure. The image sensing device is configured to sense light transmitted from a fingerprint of a finger on a display panel. The image sensing device includes a light sensing plane having a first geometric center. The light source includes a light emitting plane having a second geometric center. The first geometric center is separated from the second geometric center by a distance from 2 mm to 20 mm. The light shielding structure is disposed between the image sensing device and the light source. In examples, the optical fingerprint sensing module further includes a field angle controller to constrain light pass there through with a field angle of 5-60 degrees. A display device including an optical fingerprint sensing module is disclosed herein as well.

Abstract: Systems and methods for switching between a power supply mode and an electronic load mode are disclosed. For switching from the power supply mode to the electronic load mode, the method comprises the steps of: deactivating a power element; activating a current control module and a phase-locked loop to obtain a voltage phase of a device under test; calculating a turn-on amount of the power element according to a current setting value and the voltage phase; and causing the power element to generate a load current for the device under test. For switching from the electronic load mode to the power supply mode, the method comprises the steps of: deactivating the power element; activating a voltage control module; calculating the turn-on amount of the power element according to a voltage setting value; and causing the power element to input a corresponding voltage to the device under test.

Abstract: A semiconductor structure having a silver-indium transient liquid phase bonding joint is provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.

Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.