Abstract: A new method is provided of treating the wafer in or on the surface of which a patterned and developed layer of photoresist has been created for the purpose of creating openings in underlying layers of semiconductor material. The wafer is exposed, after the via or plug etch has been completed, to high temperature of between about 250 and 400 degrees C., using a hot plate or a furnace, in an environment of low or atmospheric pressure. The exposure of the wafer to elevated temperatures can be in an environment with or without inert gasses or with or without the presence of a base or forming gas. The dual damascene structure is then completed using a layer of DUV photo, an trench opening is created in the layer of DUV photoresist that aligns with the via opening.

Abstract: The connecting mechanism of the invention is pivotally mounted between the display device and the computer host. The connecting mechanism has an articulated arm having a first rod and a second rod connected to each other via a hinge. The ends of the first rod are respectively pivotally connected to a sidewall of the computer host and the hinge. The second rod is longer than at least half a width of the display device. A third end of the second rod is pivotally mounted on a sidewall of the display device in an appropriate location, such as a central part of the sidewall. A fourth end of the second rod is pivotally connected to the hinge. The above arrangement allows inclination and horizontal/vertical adjustments of the display device relative to the computer host.

Abstract: A method for forming a via hole, in an insulator layer, without the use of photoresist procedures, has been developed. A photosensitive, low dielectric constant layer, is used as an interlevel insulator layer, between metal interconnect structures. Direct exposure, of a specific region of the photosensitive, low dielectric constant layer, converts the a specific region of the photosensitive, low dielectric constant layer, to a material that remains insoluble in a specific solution, while an unexposed region, of the same layer, can be selectively removed, creating the desired via hole. A silicon oxide deposition, and an anisotropic dry etch procedure, are employed to protect exposed surfaces of the photosensitive, low dielectric constant layer, in the form of silicon oxide spacers, formed on the sides of the via hole, and a silicon oxide layer, overlaying the top surface of the photosensitive, low dielectric constant layer.

Abstract: A method for improving the conformity of the conductive layer in a contact hole, thus allowing for the formation of a plug in the resulting contact hole. The aforementioned method includes the following steps. First, immerse the conductive layer of the semiconductor wafer into an electrolyte. The first portion of the conductive layer at the opening of the contact hole contact with the electrolyte, the conductive layer in the contact hole is not in contact with the electrolyte due to the surface tension of the electrolyte. Second, electrically couple the electrolyte to the anode of the source power. Finally, electrically couple the conductive layer to the cathode of the power source until the first portion of the conductive layer at the opening of the contact hole is removed.