Abstract: A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

Abstract: A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which an insulating layer, conductive layer, and patterned hard mask layer are sequentially formed. The hard mask layer and the conductive layer are sequentially etched to form a trench. The exposed conductive layer is oxidized to form an oxide layer. The hard mask layer is removed. The conductive layer where not covered by the oxide layer is removed using the oxide layer as a mask.

Abstract: A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

Abstract: A method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is provided. Next, the second insulating layer is patterned to form an opening over the substrate and expose the first conductive layer. Next, a first spacer is formed over the sidewall of the lower opening and a second spacer is formed over the sidewall of the upper opening and the first spacer to make the opening has a “T” profile. Next, the exposed first conductive layer under the opening is removed, and a third spacer over the sidewall of the first spacer and the second spacer is formed. Finally, a source region is formed in the substrate under the opening and the opening is filled with a second conductive layer to form a source line.

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

Abstract: A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate electrode on a semiconductor substrate comprises a gate oxide film, a polysilicon film, a metal, a lightly doped diffusion layer, silicon dioxide spacers, and a source/drain diffusion layer. The metal is planted in an opening, where a capped silicon nitride used to occupy, on top the polysilicon film.

Abstract: A method for fabricating the control gate and floating gate of a flash memory cell. An active area is firstly formed on a semiconductor substrate, followed by the formation of a first insulating layer, a first conductive layer and a first masking layer. A first opening is then formed by partially removing the first masking layer, and a floating gate oxide layer is formed by oxidation. The remaining first masking layer is removed, followed by forming a sacrificial layer, which is then partially removed to define a second opening. The remaining sacrificial layer is used as a hard mask to partially remove the first conductive layer and the first insulating layer to form a third opening. A second insulating layer is formed to fill the third opening to form an insulating plug. Part of the first conductive layer and the first insulating layer are removed to form a floating gate, followed by forming a third insulating layer and a second conductive layer.

Abstract: The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer.

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

Abstract: The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate.

Abstract: A shallow trench isolation having an etching stop layer and its method of fabrication. The method utilizes a shield layer such as a silicon nitride layer to serve as an etching stop layer. The etching stop layer is formed in the top position of the shallow trench isolation.