Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract: A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.

Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract: The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance.

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract: The present invention disclose an iris recognition method, which utilizes a matching pursuit algorithm to simplify the extraction and reconstruction of iris features and reduce the memory space required by each iris feature vector without the penalty of recognition accuracy. The iris recognition method of the present invention comprises an iris-localization component and a pattern matching component. The iris-localization component locates the iris region via the color difference between different portions of the eyeball. The primary iris features are extracted from iris information and transformed into a sequence of iris feature vectors by a matching pursuit algorithm. Thus, the iris image can be represented by a sequence of atoms, and each atom contains base, amplitude and location. Then, the comparison between the feature vectors of two irises is performed to determine whether the two irises match.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract: A process for forming shallow trench isolation region with corner protection layer. A protection layer is formed within the opening that defines the isolation trench as part of the etching mask such that the etching rate of the protection layer is less than the mask layer and the pad insulating layer to the etchant used to remove the mask layer and pad insulating layer. The protection layer is partially removed and left adjacent to the shallow trench isolation region as a corner protection layer after removing the mask layer and pad insulating layer. Thus, the indentation next to the corner of the isolation region is avoided.

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.