Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

Abstract: A battery module includes a housing, at least one cell stack inside the housing, a tightening assembly and a thermal conductive element. The tightening assembly includes first and second plugin members. The first plugin member has a first stopping portion and a first bolt portion connected with the first stopping portion, and the first bolt portion is tapered from the first stopping portion. The second plugin member has a second stopping portion and a second bolt portion connected with the second stopping portion, and the second bolt portion is tapered from the second stopping portion. The first and second plugin members are detachably inserted into the battery module from two opposing sides of the cell stack. The thermal conductive element tightens the cell stack to the housing.

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

Abstract: A soldering process method includes the following steps. A temperature profile of generating a solder structure is measured. A final product of the solder structure is tested and recorded. A machine learning method is used to repeatedly compare and analyze a relationship between a plurality of the temperature profiles of the solder structure and a corresponding final product of the solder structure so as to find an optimal temperature profile model in accordance with quality control requirements.

Abstract: A semiconductor device and method are provided whereby a series of spacers are formed in a first region and a second region of a substrate. The series of spacers in the first region are patterned while the series of spacers in the second region are protected in order to separate the properties of the spacers in the first region from the properties of the spacers in the second region.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: The disclosure provides a battery busbar including a conductive sheet, at least two bridge portions and at least two terminal contact portions. The conductive sheet has at least one cavity portion. Each of the at least two bridge portions has a first end and a second end which are opposite to each other, and the first ends of the bridge portions are respectively connected to different sides of the at least one cavity portion. The terminal contact portions are spaced apart from each other and are respectively connected to the second ends of the bridge portions. A width direction is defined to be substantially perpendicular to a line passing through the first end and the second end of one of the at least two bridge portions; along the width direction, a width of the bridge portion is smaller than a width of the terminal contact portion.

Abstract: A battery system, a control method of a cell balance procedure and a calculation method of a balance charge capacity are provided. The battery system includes a plurality of battery units, a communication bus and a host control unit. Each battery unit includes a plurality of cells, an isolated charger, a switch array circuit, a balance slave switch and a balance slave controller. The host control unit includes a balance host controller, a balance host switch and a system current measurement unit. When the error between a balance detection voltage calculated by each balance slave controller and the balance detection voltage calculated by the balance host controller is less than a predetermined value, the balance host switch and the corresponding balance slave switches are in conduction and the specified plurality cells of battery system are charged for keeping cell balance purpose.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a memory cell, a first logic transistor, and a second logic transistor. The semiconductor substrate includes a memory region and a logic region. The memory cell is disposed in the memory region. The first logic transistor is disposed in the memory region and disposed adjacent to the memory cell. The second logic transistor is disposed in the logic region. The first logic transistor is configured to control operation of the memory cell in response to a memory control signal provided by the second logic transistor.

Abstract: A fireproof battery module including a plurality of battery cells and at least one fireproof layer. The battery cells are electrically connected to one another. The at least one fireproof layer is located between two of the plurality of battery cells that are adjacent to each other. The fireproof layer includes a heat absorbing part and a heat insulation part that are connected to each other. The heat absorbing part includes a vaporizable material and a thermal conductivity of the heat insulation part is lower than a thermal conductivity of the heat absorbing part.

Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

Abstract: A battery module includes a housing, at least one cell stack inside the housing, a tightening assembly and a thermal conductive element. The tightening assembly includes first and second plugin members. The first plugin member has a first stopping portion and a first bolt portion connected with the first stopping portion, and the first bolt portion is tapered from the first stopping portion. The second plugin member has a second stopping portion and a second bolt portion connected with the second stopping portion, and the second bolt portion is tapered from the second stopping portion. The first and second plugin members are detachably inserted into the battery module from two opposing sides of the cell stack. The thermal conductive element tightens the cell stack to the housing.