Patents by Inventor Chung-Te Lin

Chung-Te Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733352
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien
  • Patent number: 10734580
    Abstract: A memory device includes an inter-layer dielectric (ILD) layer, a metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a bottom electrode via. The metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer. The memory cell is over the metal-containing compound layer and includes a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The bottom electrode via connects the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Han-Ting Tsai, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 10727177
    Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue
  • Publication number: 20200235292
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MU) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Ren DAI, Chung-Ju LEE, Chung-Te LIN, Chih-Wei LU, Hsi-Wen TIEN, Tai-Yen PENG, Chien-Min LEE, Wei-Hao LIAO
  • Publication number: 20200226316
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung LIN, Chung-Hsing Wang, Yuan-Te Hou
  • Publication number: 20200226229
    Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.
    Type: Application
    Filed: September 27, 2019
    Publication date: July 16, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hua LIU, Yun-Xiang LIN, Yuan-Te HOU, Chung-Hsing WANG
  • Publication number: 20200219973
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin structure over a substrate, and the fin structure includes alternately stacked semiconductor material layers and sacrificial layers. The method further includes forming a dummy gate structure, recessing the fin structure to form an opening, forming first source/drain spacers on sidewalls of the sacrificial layers by performing a first atomic layer deposition (ALD) process, and forming source/drain structure in the opening. The method further includes removing the dummy gate structure and the sacrificial layers to expose the semiconductor material layers and forming a gate structure wrapping around the semiconductor material layers.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark VAN DAL, Gerben DOORNBOS, Chung-Te LIN
  • Patent number: 10707199
    Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Patent number: 10700125
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Patent number: 10671788
    Abstract: A method includes accessing a design data of an integrated circuit (IC), the design data including a plurality of layers. For each of the layers, the method performs: assigning a bin size of the respective layer based on a layout property of the respective layer; and performing a bin-based feature allocation according to the assigned bin size. The method also includes updating the design data according to the bin-based feature allocation. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Publication number: 20200152617
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan CHANG, Sheng-Hsiung CHEN, Ting-Wei CHIANG, Chung-Te LIN, Jung-Chan YANG, Lee-Chung LU, Po-Hsiang HUANG, Chun-Chen CHEN
  • Publication number: 20200144251
    Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: May 7, 2020
    Inventors: Wei-Chih WEN, Han-Ting TSAI, Chung-Te LIN
  • Patent number: 10644231
    Abstract: A method for fabricating a memory device includes forming a resistance switching element over a bottom electrode; forming a top electrode over the resistance switching element; forming a first spacer covering a sidewall of the resistance switching element; forming a second spacer surrounding the first spacer and exposing the top electrode; and forming a metallization pattern connected with the top electrode and the second spacer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 10642949
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Publication number: 20200135806
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Application
    Filed: September 4, 2019
    Publication date: April 30, 2020
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Publication number: 20200136038
    Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric lower, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.
    Type: Application
    Filed: May 15, 2019
    Publication date: April 30, 2020
    Inventors: Mauricio Manfrini, Chung-Te Lin, Gerben Doornbos, Marcus Johannes Henricus van Dal
  • Patent number: 10636963
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ren Dai, Chung-Ju Lee, Chung-Te Lin, Chih-Wei Lu, Hsi-Wen Tien, Tai-Yen Peng, Chien-Min Lee, Wei-Hao Liao
  • Publication number: 20200127110
    Abstract: A method includes providing a structure having a substrate, a gate structure over the substrate, a sacrificial spacer over a sidewall of the gate structure, a source/drain feature over the substrate and adjacent to the gate structure; forming a dielectric layer over the gate structure, the sacrificial spacer, and the source/drain feature; with the dielectric layer over the gate structure, the sacrificial spacer, and the source/drain feature, forming a contact extending through the dielectric layer to the source/drain feature; removing the dielectric layer to expose the sacrificial spacer; etching the sacrificial spacer to form a trench; and depositing an inter-layer dielectric (ILD) layer, wherein the ILD layer caps the trench, thereby defining an air gap inside the trench.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
  • Publication number: 20200126966
    Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Tung-Heng HSIEH, Hui-Zhong ZHUANG, Chung-Te LIN, Sheng-Hsiung WANG, Ting-Wei CHIANG, Li-Chun TIEN
  • Publication number: 20200127046
    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 23, 2020
    Inventors: Sheng-Chih Lai, Chung-Te Lin, Min Cao, Randy Osborne