Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.

Abstract: An integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate and includes a first dielectric layer and a memory module. The memory module includes a first memory device, a second memory device, and a third memory device. The first memory device is embedded in the first dielectric layer. The second memory device is disposed aside the first memory device and is embedded in the first dielectric layer. The first memory device, the second memory device, and the third memory device are different types of memory devices.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a memory device disposed within an inter-level dielectric (ILD) structure over a substrate. The memory device has a data storage structure between a first electrode and a second electrode. A first unidirectional current controller and a second unidirectional current controller are disposed within the ILD structure. A conductor arranged between the first unidirectional current controller and the data storage structure along a first conductive path and further arranged between the second unidirectional current controller and the data storage structure along a second conductive path. A part of the first conductive path overlaps a part, but not all, of the second conductive path.

Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.

Abstract: A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A memory device is formed in an interconnect structure over a substrate. Forming the memory device includes forming an alternating stack of dielectric material layers and conductive material layers, wherein the alternating stack includes a memory array region and a staircase region adjacent to the memory array region; forming a trench on the memory array region of the alternating stack; forming a data storage layer, channel layers, bit line pillars, and source line pillars in the trench; and performing patterning processes to from a staircase structure on the staircase region. The staircase structure steps downward from a first direction and makes a 180-degree turn to step downward in a second direction opposite to the first direction.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.