Patents by Inventor Chung-Te Lin

Chung-Te Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230380182
    Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Hui-Hsien WEI, Chung-Te LIN, Han-Ting TSAI, Tai-Yen PENG, Yu-Teng DAI, Chien-Min LEE, Sheng-Chih LAI, Wei-Chih WEN
  • Publication number: 20230371259
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a first access line extending in a horizontal direction, a first column of memory cells over the first access line, a second column of memory cells adjacent to the first column of memory cells, and a second access line over the first column of memory cells and the second column of memory cells and extending in the horizontal direction. The first column of memory cells includes a first gate line electrically connected to the first access line, and the second column of memory cells includes a second gate line electrically connected to the second access line.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih LAI, Chung-Te LIN
  • Publication number: 20230371261
    Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Publication number: 20230371272
    Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
  • Publication number: 20230369107
    Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Li-Shyue Lai, Gao-Ming Wu, Katherine H. Chiang, Chung-Te Lin
  • Publication number: 20230371273
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20230371278
    Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Mauricio MANFRINI, Chung-Te LIN
  • Publication number: 20230369429
    Abstract: A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Katherine H. CHIANG, Chung-Te LIN
  • Publication number: 20230369420
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin
  • Publication number: 20230371239
    Abstract: A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Katherine H. CHIANG, Ken-Ichi GOTO, Chia Yu LING, Neil MURRAY, Chung-Te LIN
  • Patent number: 11818894
    Abstract: Provided is a memory cell including a channel material contacting a source line and a bit line; a ferroelectric (FE) material contacting the channel material; and a word line contacting the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer; and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.
    Type: Grant
    Filed: August 29, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Ling, Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11818896
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
  • Patent number: 11818882
    Abstract: In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Publication number: 20230363175
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20230363173
    Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rainer Yen-Chieh Huang, Han-Ting Tsai, Tsann Lin, Kuo-Chang Chiang, Min-Kun Dai, Chung-Te Lin
  • Publication number: 20230363181
    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Sheng-Chih Lai, Chung-Te Lin, Min Cao, Randy Osborne
  • Publication number: 20230363180
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a magnetic tunnel junction (MTJ) disposed on a first electrode within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is electrically coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is electrically coupled to the first electrode. The first unipolar selector laterally extends between a first vertical line intersecting the MTJ and the substrate and a second vertical line intersecting the second unipolar selector and the substrate.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Inventors: Katherine H. Chiang, Chung-Te Lin, Mauricio Manfrini
  • Publication number: 20230363171
    Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Publication number: 20230361221
    Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Inventors: Yong-Jie Wu, Hui-Hsien Wei, Yen-Chung Ho, Mauricio Manfrini, Chia-Jung Yu, Chung-Te Lin, Pin-Cheng Hsu
  • Publication number: 20230360698
    Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i?1√óC. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: Katherine H. CHIANG, Chung-Te LIN