Abstract: The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: An analog input device including at least one mounting panel and a matrix of analog push button assemblies mounted thereon. Each analog push button assembly including an analog pressure sensor including a pressure reception arrangement having an optical sensing sub-arrangement configured to measure an amount of light varied according to a pressure sensed at the pressure reception arrangement and an output terminal for outputting an analog signal corresponding to the amount of light measured, and a plunger element configured to exert the pressure on the pressure reception arrangement. The analog input device may include a multiplexer including an input side coupled to the push button assemblies and an output side; an analog-to-digital converter coupled to the output side of the multiplexer; a processor coupled to the analog-to-digital converter and configured to output a data packet; and a communication interface configured to transmit the data packet to a host computing device.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: A semiconductor device includes a channel portion disposed on and spaced apart from a substrate, a gate dielectric which includes an upper dielectric region disposed on the channel portion, a first inner gate structure disposed between the substrate and the upper dielectric region, and an outer gate structure including an outer work-function portion and a cap portion. The outer work-function portion covers the upper dielectric region and the first inner gate structure. The cap portion covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure. The first inner gate structure includes a first work-function material and a conductive material that is different from the first work-function material. The outer work-function portion includes a second work-function material that is different from the conductive material.

Abstract: An optical composite structure includes first, second and third prism sheets. The first prism sheet has a first light incident surface and a first light exit surface opposite to each other. The second prism sheet has a second light incident surface facing the first light exit surface and a second light exit surface opposite to the second light incident surface, and includes a haze layer having the second light incident surface and a prism layer which is stacked on the haze layer and which has the second light exit surface. The third prism sheet has a third light incident surface facing the second light exit surface, and includes a haze layer and a prism layer stacked on the haze layer of the third prism sheet. The haze layer of the third prism sheet has a haze greater than a haze of the haze layer of the second prism sheet.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: A memory cell structure includes a transistor structure and a capacitor structure, where the capacitor structure includes a hydrogen absorption layer. The hydrogen absorption layer absorbs hydrogen, which prevents or reduces the likelihood of the hydrogen diffusing into an underlying metal-oxide channel of the transistor structure. In this way, the hydrogen absorption layer minimizes and/or reduces the likelihood of hydrogen contamination in the metal-oxide channel, which may enable a low current leakage to be achieved for the memory cell structure and reduces the likelihood of data corruption and/or failure of the memory cell structure, among other examples.

Abstract: A production line operation forecast method and a production line operation forecast system are provided. The production line operation forecast method includes the following steps: obtaining an online production line work-in-process map at a time point, generating candidate simulated dispatch decisions based on the online production line work-in-process map, and inferring production-line work-in-process map changes of the candidate simulated dispatch decisions at a next time point; inputting the production-line work-in-process map changes to a forecast model, such that the forecast model outputs simulated production line operation health indicators of the candidate simulated dispatch decisions at the next time point; and selecting one of the candidate simulated dispatch decisions as a scheduling dispatch decision.

Abstract: A device comprises a support net with nodes, wherein each node comprises a HTS photovoltaic-magnetic cell, wherein alignments of the HTS photovoltaic-magnetic cells are arranged with N-S in parallel alignment. A device comprises a tether comprising a plurality of HTS solenoids and a sheath, wherein a solenoid of the plurality of HTS solenoids comprises a high temperature superconducting material and reinforcing fiber. A device comprises propulsion ball or plate with tail, injected in propulsion channel; HTS solenoids disposed along walls of propulsion channel, wherein the propulsion ball or plate with tail are moved through the propulsion channel using magnetic field generated by HTS solenoids; and a collection channel.

Abstract: Various embodiments for systems and methods for cooperative driving of connected autonomous vehicles using responsibility-sensitive safety (RSS) rules are disclosed herein. The CAV system integrates proposed RSS rules with CAV's motion planning algorithm to enable cooperative driving of CAVs. The CAV system further integrates a deadlock detection and resolution system for resolving traffic deadlocks between CAVs. The CAV system reduces redundant calculation of dependency graphs.

Abstract: An electronic device includes a surface structure. The surface structure has a curved surface and includes a substrate, a first conductive line, and a first dielectric pattern. The first conductive line is disposed above the substrate. The first dielectric pattern is disposed above the first conductive line and overlaps with the first conductive line. The surface structure has a first region and a second region. The first dielectric pattern in the first region has a first average width, the first dielectric pattern in the second region has a second average width, and the first average width is different from the second average width.

Abstract: An electrical connection device includes a mother board and a daughter board. The mother board includes a first board body with at least one cavity and a first electrical contact printed on the first board body. The daughter board includes a second board body and a second electrical contact printed on the second board body. At least one of the daughter board and the mother board includes at least one contour feature integrally formed with at least one of the first board body and the second board body. When the second board body is inserted into the at least one cavity of the first board body, the second electrical contact is electrically connected to the first electrical contact, and the daughter board is positioned in the mother board through the at least one contour feature.

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.