Patents by Inventor Chung Wei

Chung Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240056076
    Abstract: An analog input device including at least one mounting panel and a matrix of analog push button assemblies mounted thereon. Each analog push button assembly including an analog pressure sensor including a pressure reception arrangement having an optical sensing sub-arrangement configured to measure an amount of light varied according to a pressure sensed at the pressure reception arrangement and an output terminal for outputting an analog signal corresponding to the amount of light measured, and a plunger element configured to exert the pressure on the pressure reception arrangement. The analog input device may include a multiplexer including an input side coupled to the push button assemblies and an output side; an analog-to-digital converter coupled to the output side of the multiplexer; a processor coupled to the analog-to-digital converter and configured to output a data packet; and a communication interface configured to transmit the data packet to a host computing device.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 15, 2024
    Inventors: Chung Wei LEE, Thuan Teck TAN, Wenliang YANG, Alvin SIM, Kok Kiong LOW
  • Patent number: 11901361
    Abstract: A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang
  • Publication number: 20240041810
    Abstract: This disclosure provides pharmaceutical compositions comprising amino acid entities and uses thereof. Methods for improving liver function and for treating liver diseases comprising administering an effective amount of the compositions to a subject in need thereof are also disclosed.
    Type: Application
    Filed: March 8, 2023
    Publication date: February 8, 2024
    Inventors: Michael Hamill, Raffi Afeyan, Chung-Wei Lee, Harry Luithardt
  • Publication number: 20240048965
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node, a network assistant information (NAI) message identifying a set of characteristics of a network connection. The UE may communicate with the network node using a communication configuration associated with the set of characteristics of the network connection. Numerous other aspects are described.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Inventors: Kai-Chun CHENG, Jen-Chun CHANG, Kuhn-Chang LIN, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yu-Chieh HUANG, Chun-Hsiang CHIU, ChihHung HSIEH, Chung Wei LIN, Yeong Leong CHOO
  • Patent number: 11894460
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11894367
    Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11886073
    Abstract: Embodiments of a display device are described. A display device includes a backlight unit having a light source and a liquid crystal display (LCD) module. The light source is configured to emit a primary light having a first peak wavelength. The LCD module includes a first sub-pixel having a phosphor film and a second sub-pixel having a non-phosphor film. The phosphor film is configured to receive a first portion of the primary light and to convert the first portion of the primary light to emit a secondary light having a second peak wavelength that is different from the first peak wavelength. The non-phosphor film is configured to receive a second portion of the primary light and to optically modify the second portion of the primary light to emit an optically modified primary light having a third peak wavelength that is different from the first and second peak wavelengths.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: January 30, 2024
    Assignee: SHOEI CHEMICAL INC.
    Inventors: Ernest Chung-Wei Lee, Charles Hotz
  • Publication number: 20240032274
    Abstract: A memory device includes a semiconductor substrate. The memory device includes a stack of channel layers over the semiconductor substrate, each channel layer including an oxide material. The memory device includes a word line structure interleaved with the stack of channel layers. The memory device includes a source feature and a drain feature on both sides of the stack of channel layers.
    Type: Application
    Filed: January 30, 2023
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Chun Liou, Chia-En Huang, Ya-Yun Cheng, Chung-Wei Wu
  • Publication number: 20240019915
    Abstract: A computer-implemented method of managing a thermal policy of an information handling system involves identifying a first power associated with a central processing unit (CPU) of the information handling system, identifying a first time duration of a first workload associated with the CPU, accessing a table indicating, for combinations of workload time durations and CPU power, a ramp rate and a thermal management mode, comparing the first power and the first time duration with the table to identify a first ramp rate and a first thermal management mode associated with the first power and the first time duration, and placing the CPU and a fan of the information handling system in the first thermal management mode and adjusting a fan speed of the fan based on the first ramp rate.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 18, 2024
    Inventors: TseAnGino Chu, Ting-Chiang Huang, Chung-Wei Wang, Qinghong He
  • Patent number: 11871775
    Abstract: A method of inhibiting oral pathogens comprising administering to a subject in need thereof an effective amount of Lactobacillus strain-containing food composite, medical composite and oral cleaning composite. The food composite, medical composite and oral cleaning composite comprises at least one Lactobacillus strain, which is at least one isolated Lactobacillus strain selected from a group including Lactobacillus acidophilus F-1 strain, CCTCC NO: M2011124; Lactobacillus salivarius subsp. salicinius AP-32 strain, CCTCC NO: M2011127; Lactobacillus reuteri GL-104 strain, CCTCC NO: M209138; Lactobacillus paracasei GL-156 strain, CCTCC NO: M2014590; Lactobacillus helveticus RE-78 strain, CGMCC No. 13513; Lactobacillus rhamnosus CT-53 strain, CCTCC NO: M2011129; and Lactobacillus paracasei ET-66 strain, CGMCC No. 13514, which are respectively preserved in China Center for Type Culture Collection (CCTCC) and China General Microbiological Culture Collection Center (CGMCC).
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 16, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Pei-Shan Hsieh, Chung-Wei Kuo, Yi-Chun Tsai, Hsieh-Hsun Ho, Yi-Wei Kuo
  • Publication number: 20240014265
    Abstract: The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.
    Type: Application
    Filed: March 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11869955
    Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer of the I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the core gate all around transistor.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11861283
    Abstract: A placement method for integrated circuit design is provided. Each net is considered as a soft module. The net will receive a larger penalty if it covers more routing congested regions. Therefore, it is easier to move the nets away from routing congested regions. In addition, to relieve local congestion, a novel inflation method is proposed to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. Accordingly, it can get better routability and wirelength.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: January 2, 2024
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Fa Tsai, Che-Li Lin, Chia-Min Lin, Chung-Wei Huang, Liang-Chi Zane
  • Patent number: 11862700
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chun-Fu Lu, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11862633
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
  • Patent number: 11862525
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: January 2, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
  • Patent number: 11863175
    Abstract: An analog input device including at least one mounting panel and a matrix of analog push button assemblies mounted thereon. Each analog push button assembly including an analog pressure sensor including a pressure reception arrangement having an optical sensing sub-arrangement configured to measure an amount of light varied according to a pressure sensed at the pressure reception arrangement and an output terminal for outputting an analog signal corresponding to the amount of light measured, and a plunger element configured to exert the pressure on the pressure reception arrangement. The analog input device may include a multiplexer including an input side coupled to the push button assemblies and an output side; an analog-to-digital converter coupled to the output side of the multiplexer; a processor coupled to the analog-to-digital converter and configured to output a data packet; and a communication interface configured to transmit the data packet to a host computing device.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 2, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Chung Wei Lee, Thuan Teck Tan, Wenliang Yang, Alvin Sim, Kok Kiong Low
  • Publication number: 20230420506
    Abstract: A method includes forming a channel region above a (110)-orientated substrate and having a length extending in a <100> direction; epitaxial growing a plurality of source/drain regions on either side the channel region; forming a gate structure surrounding the channel region; forming a plurality of source/drain contacts on the source/drain regions.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju LEE, Chun-Fu CHENG, Chung-Wei WU, Zhiqiang WU
  • Patent number: 11855143
    Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: D1011426
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: January 16, 2024
    Assignee: HTC Corporation
    Inventors: Pei-Pin Huang, Chang-Hua Wei, Chung-Wei Li, Yu-Lin Huang