Patents by Inventor Chung-Yao Chang

Chung-Yao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154021
    Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 9, 2024
    Inventors: TING-CHANG CHANG, Wei-Chen Huang, Shih-Kai Lin, Yong-Ci Zhang, Sheng-Yao Chou, Chung-Wei Wu, Po-Hsun Chen
  • Patent number: 11927303
    Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 12, 2024
    Assignee: HTC Corporation
    Inventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
  • Publication number: 20230283309
    Abstract: The present invention discloses a signal receiving apparatus having phase compensation mechanism. A first and a second receiving path of a receiving circuit perform frequency down-conversion and analog-to-digital conversion on an input signal to generate a first and a second receiving signals. The first and the second receiving paths uses a RF training signal generated by a RF training signal generation circuit as the input signal when a phase compensation is performed, and use a data signal from an antenna circuit as the input signal when a beamforming signal receiving is performed. A phase difference calculation circuit of the receiving circuit performs cross-correlation operation on the first and the second receiving signals to generate a compensation signal according to a phase difference between the first and the second receiving paths.
    Type: Application
    Filed: December 6, 2022
    Publication date: September 7, 2023
    Inventors: HAO-HAN HSU, CHUAN-HU LIN, CHUNG-YAO CHANG
  • Patent number: 11705934
    Abstract: A wireless communication chip includes an analog front-end circuit and a baseband circuit. The analog front-end circuit includes a first transceiver circuit and a second transceiver circuit, wherein the first transceiver circuit is arranged to transmit or receive signals through a first antenna, and the second transceiver circuit is arranged to transmit or receive signals through a second antenna. The baseband circuit is arranged to control the first transceiver circuit to use a first band or a second band for communication, and/or to control the second transceiver circuit to use the first band or the second band for communication. The baseband circuit controls the first transceiver circuit and the second transceiver circuit so that the analog front-end circuit alternately performs 2T2R in the first band and 2T2R in the second band.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: July 18, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hao-Han Hsu, Chung-Yao Chang
  • Publication number: 20230189327
    Abstract: A wireless device includes a time-sensitive queue, an access category queue, a controller, and a transmitter. The access category queue is associated with an access category and a link. The controller is coupled to the access category queue, and is used to acquire a transmission opportunity according to a set of contention parameters of the access category. The transmitter is coupled to the controller and the time-sensitive queue, and is used to when a transmission opportunity is acquired, if the time-sensitive queue contains data, generate a data frame according to the data in the time-sensitive queue, and transmit the data to another wireless device via a link.
    Type: Application
    Filed: June 23, 2022
    Publication date: June 15, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Publication number: 20220337283
    Abstract: A wireless communication chip includes an analog front-end circuit and a baseband circuit. The analog front-end circuit includes a first transceiver circuit and a second transceiver circuit, wherein the first transceiver circuit is arranged to transmit or receive signals through a first antenna, and the second transceiver circuit is arranged to transmit or receive signals through a second antenna. The baseband circuit is arranged to control the first transceiver circuit to use a first band or a second band for communication, and/or to control the second transceiver circuit to use the first band or the second band for communication. The baseband circuit controls the first transceiver circuit and the second transceiver circuit so that the analog front-end circuit alternately performs 2T2R in the first band and 2T2R in the second band.
    Type: Application
    Filed: November 23, 2021
    Publication date: October 20, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Hao-Han Hsu, Chung-Yao Chang
  • Patent number: 11197201
    Abstract: This invention discloses a method for controlling a wireless communication device to reduce the number of retry times of data packets during transmission. The method includes steps of: using a first packet length to generate and transmit data packets; counting retry times of data packets in a predetermined time period and generating a result accordingly; and using a second packet length smaller than said first packet length to generate and transmit data packets when said result is greater than a predetermined value.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: December 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Nan Lin, Wei-Chi Lai, Shen-Chung Lee, Chung-Yao Chang, Wei-Hsuan Chang
  • Patent number: 11018801
    Abstract: A method for performing bit level management in a wireless local area network (WLAN) system, transmitter and receiver are provided. The method includes: calculating respective bit counts of one or more padding fields located in one or more locations within a packet in a transmitter within the WLAN system, respectively; and according to the respective bit counts of the one or more padding field, filling one or more sets of valid data corresponding to at least one predetermined bit count into the one or more padding fields, to replace one or more sets of redundant data. In addition, when a receiver within the WLAN system receives the packet that has the one or more sets of valid data, the WLAN system utilizes the one or more sets of valid data to enhance overall performance of the WLAN system.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Wen-Yung Lee
  • Patent number: 10958294
    Abstract: The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Chieh Huang, Chung-Yen Liu, Yi-Syun Yang, Chung-Yao Chang
  • Patent number: 10826541
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 3, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuei-Cheng Chan, Chung-Yao Chang, Wei-Chieh Huang
  • Patent number: 10749712
    Abstract: A bandwidth detection device comprises a receiving circuit, for receiving a first plurality of frequency-domain signals on a first subchannel; a filter circuit, coupled to the receiving circuit, for transferring the first plurality of frequency-domain signals to a first plurality of filtered frequency-domain signals according to a filter function; and a processing circuit, coupled to the filter circuit, for comparing the first plurality of frequency-domain signals with the first plurality of filtered frequency-domain signals, to determine whether the first subchannel comprises first transmitted data.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 18, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Jung Wu, Yi-Syun Yang, Chung-Yao Chang
  • Patent number: 10742284
    Abstract: A wireless communication method applied to a beamformer includes: receiving a plurality of reference information corresponding to a plurality of stations, respectively; calculating an evaluation value for each of the stations according to at least one reference information of the plurality of reference information; and comparing a plurality of evaluation values respectively corresponding to the plurality of stations, to select specific stations from the plurality of stations for performing beamforming.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 11, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Wei Hsin, Chung-Yao Chang
  • Patent number: 10720944
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: July 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuei-Cheng Chan, Chung-Yao Chang, Wei-Chieh Huang
  • Patent number: 10708032
    Abstract: Disclosed is a symbol timing determining device including: a symbol timing detecting circuit detecting a reception signal to obtain a first symbol timing, and shifting the first symbol timing to obtain a second symbol timing; an estimation signal generating circuit processing the reception signal according to the first and the second symbol timings respectively, so as to obtain a first and a second channel estimation frequency-domain signals; a channel estimation impulse response signal generating circuit generating a first and a second channel estimation impulse response time-domain signals according to the first and the second channel estimation frequency-domain signals respectively; a power measuring circuit measuring the energy of the first and the second channel estimation impulse response time-domain signals according to a predetermined signal region respectively; and a decision circuit selecting one of the first and the second symbol timings according to a relation of the measured energy.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chuan-Hu Lin, Chung-Yao Chang
  • Publication number: 20200145883
    Abstract: This invention discloses a method for controlling a wireless communication device to reduce the number of retry times of data packets during transmission. The method includes steps of: using a first packet length to generate and transmit data packets; counting retry times of data packets in a predetermined time period and generating a result accordingly; and using a second packet length smaller than said first packet length to generate and transmit data packets when said result is greater than a predetermined value.
    Type: Application
    Filed: January 7, 2020
    Publication date: May 7, 2020
    Inventors: YU-NAN LIN, WEI-CHI LAI, SHEN-CHUNG LEE, CHUNG-YAO CHANG, WEI-HSUAN CHANG
  • Publication number: 20200112325
    Abstract: The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.
    Type: Application
    Filed: July 23, 2019
    Publication date: April 9, 2020
    Inventors: Wei-Chieh Huang, Chung-Yen Liu, Yi-Syun Yang, Chung-Yao Chang
  • Publication number: 20200112387
    Abstract: A method for performing bit level management in a wireless local area network (WLAN) system, transmitter and receiver are provided. The method includes: calculating respective bit counts of one or more padding fields located in one or more locations within a packet in a transmitter within the WLAN system, respectively; and according to the respective bit counts of the one or more padding field, filling one or more sets of valid data corresponding to at least one predetermined bit count into the one or more padding fields, to replace one or more sets of redundant data. In addition, when a receiver within the WLAN system receives the packet that has the one or more sets of valid data, the WLAN system utilizes the one or more sets of valid data to enhance overall performance of the WLAN system.
    Type: Application
    Filed: May 23, 2019
    Publication date: April 9, 2020
    Inventors: Chung-Yao Chang, Wen-Yung Lee
  • Patent number: 10595232
    Abstract: This invention discloses a method for controlling a wireless communication device to transmit data packets. The method includes steps of: transmitting data packets; counting retry times of data packets in a predetermined time period and generating a result accordingly; comparing said result with a predetermined value and generating a comparison result accordingly; and reducing transmission time of data packets according to said comparison result.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Nan Lin, Wei-Chi Lai, Shen-Chung Lee, Chung-Yao Chang, Wei-Hsuan Chang
  • Publication number: 20200076646
    Abstract: A bandwidth detection device comprises a receiving circuit, for receiving a first plurality of frequency-domain signals on a first subchannel; a filter circuit, coupled to the receiving circuit, for transferring the first plurality of frequency-domain signals to a first plurality of filtered frequency-domain signals according to a filter function; and a processing circuit, coupled to the filter circuit, for comparing the first plurality of frequency-domain signals with the first plurality of filtered frequency-domain signals, to determine whether the first subchannel comprises first transmitted data.
    Type: Application
    Filed: May 8, 2019
    Publication date: March 5, 2020
    Inventors: Cheng-Jung Wu, Yi-Syun Yang, Chung-Yao Chang
  • Publication number: 20200028526
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.
    Type: Application
    Filed: June 17, 2019
    Publication date: January 23, 2020
    Inventors: KUEI-CHENG CHAN, CHUNG-YAO CHANG, WEI-CHIEH HUANG