Patents by Inventor Chung-Yao Chang

Chung-Yao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200028525
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.
    Type: Application
    Filed: June 17, 2019
    Publication date: January 23, 2020
    Inventors: KUEI-CHENG CHAN, CHUNG-YAO CHANG, WEI-CHIEH HUANG
  • Patent number: 10461776
    Abstract: A receiving device comprises an iterative decoder, a first determination unit and a control unit. The iterative decoder is for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration. The first determination unit is for determining whether the plurality of decoded signals diverge, to generate a first determination result. The control unit is for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 29, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chuan-Hu Lin, Wei-Chieh Huang, Chia-Chun Tsui, Chung-Yao Chang
  • Patent number: 10382163
    Abstract: A receiving device comprises a channel estimation unit, for generating a plurality of channel estimates according to a plurality of reference signals; an eigenvalue computation unit, coupled to the channel estimation unit, for generating at least one eigenvalue corresponding to the plurality of channel estimates according to the plurality of channel estimates; a channel compensation unit, coupled to the eigenvalue computation unit, for generating a correlation compensation value for compensating the plurality of channels according to the at least one eigenvalue; a channel capacity computation unit, coupled to the eigenvalue computation unit and the channel compensation unit, for generating a channel capacity according to the at least one eigenvalue and the correlation compensation value; and a selection unit, coupled to the channel capacity computation unit, for determining a modulation and coding scheme (MCS) according to the channel capacity.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 13, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chuan-Hu Lin, Chung-Yao Chang
  • Patent number: 10355802
    Abstract: A method of cell search for a mobile device in a wireless communication system is provided. The method comprises performing a reception timing detection procedure, to obtain at least a possible reception time for a primary synchronization signal (PSS), performing a PSS hypothesis procedure, to generate three frequency-domain PSS sequences according to three root indexes each corresponding to a physical layer identity, and performing a secondary synchronization signal (SSS) coherent detection procedure, to calculate a SSS sequence according to each of the at least a possible reception time with the three frequency-domain PSS sequences, to obtain a physical layer cell identity group corresponding to the SSS sequence.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 16, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Publication number: 20190215143
    Abstract: Disclosed is a symbol timing determining device including: a symbol timing detecting circuit detecting a reception signal to obtain a first symbol timing, and shifting the first symbol timing to obtain a second symbol timing; an estimation signal generating circuit processing the reception signal according to the first and the second symbol timings respectively, so as to obtain a first and a second channel estimation frequency-domain signals; a channel estimation impulse response signal generating circuit generating a first and a second channel estimation impulse response time-domain signals according to the first and the second channel estimation frequency-domain signals respectively; a power measuring circuit measuring the energy of the first and the second channel estimation impulse response time-domain signals according to a predetermined signal region respectively; and a decision circuit selecting one of the first and the second symbol timings according to a relation of the measured energy.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 11, 2019
    Inventors: CHUAN-HU LIN, CHUNG-YAO CHANG
  • Patent number: 10270558
    Abstract: The present disclosure includes an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a search value according to a communication index and a modulation type or determine the search value according to a predetermined value, in which the communication index is related to a reception signal or a derivative thereof, the search value is associated with a search range, and a number of candidate signal value(s) in the search range is not greater than a number of all candidate signal values of the modulation type. The ML detecting circuit is configured to execute an ML calculation according to the search value and one of the reception signal and the derivative thereof, so as to calculate a log likelihood ratio of every candidate signal value in the search range.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 23, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yao Chang, Wei-Chieh Huang, Yi-Syun Yang
  • Patent number: 10256173
    Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 9, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jun-Chieh Wu, Yu-Hsiang Chao, Chung-Yao Chang, Chun-Cheng Kuo
  • Patent number: 10171185
    Abstract: A receiving device comprises a signal detection unit, a reliability unit coupled to the signal detection unit and a decoding unit coupled to the signal detection unit and the reliability unit. The signal detection unit is for receiving a plurality of compensated symbols on a plurality of subcarriers, to generate a plurality of soft information and a plurality demodulated symbols of the plurality of compensated symbols according to the plurality of compensated symbols. The reliability unit is for generating a plurality of weights of the plurality of soft information according to a plurality of reliability information of the plurality of subcarriers. The decoding unit is for decoding the plurality of demodulated symbols according to the plurality of soft information and the plurality of weights, to generate a plurality of decoded bits.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 1, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Yi-Syun Yang, Kai-Jie Yang
  • Publication number: 20180248563
    Abstract: A receiving device comprises an iterative decoder, for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration; a first determination unit, coupled to the iterative decoder, for determining whether the plurality of decoded signals diverge, to generate a first determination result; and a control unit, coupled to the first determination unit, for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.
    Type: Application
    Filed: January 4, 2018
    Publication date: August 30, 2018
    Inventors: Chuan-Hu Lin, Wei-Chieh Huang, Chia-Chun Tsui, Chung-Yao Chang
  • Publication number: 20180234160
    Abstract: The present disclosure provides a demodulation method. The demodulation method includes obtaining a received signal; determining whether a multiuser interference is smaller than a threshold; performing a first signal detection operation on the received signal if the multiuser interference is smaller than the threshold, in which the first signal detection operation detects a single layer of spatial data in the received signal; and performing a second signal detection operation on the received signal if the multiuser interference is greater than the threshold, in which the second signal detection operation detects multiple layers of spatial data in the received signal.
    Type: Application
    Filed: August 28, 2017
    Publication date: August 16, 2018
    Inventors: Chung-Yao Chang, Wei-Chieh Huang, Yi-Syun Yang
  • Publication number: 20180205489
    Abstract: A receiving device comprises a channel estimation unit, for generating a plurality of channel estimates according to a plurality of reference signals; an eigenvalue computation unit, coupled to the channel estimation unit, for generating at least one eigenvalue corresponding to the plurality of channel estimates according to the plurality of channel estimates; a channel compensation unit, coupled to the eigenvalue computation unit, for generating a correlation compensation value for compensating the plurality of channels according to the at least one eigenvalue; a channel capacity computation unit, coupled to the eigenvalue computation unit and the channel compensation unit, for generating a channel capacity according to the at least one eigenvalue and the correlation compensation value; and a selection unit, coupled to the channel capacity computation unit, for determining a modulation and coding scheme (MCS) according to the channel capacity.
    Type: Application
    Filed: September 6, 2017
    Publication date: July 19, 2018
    Inventors: Chuan-Hu Lin, Chung-Yao Chang
  • Patent number: 9954647
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 24, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yao Chang, Chuan-Hu Lin, Yi-Syun Yang
  • Patent number: 9893841
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first-layer search value. The ML detecting circuit is configured to carry out the following steps: selecting first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, and adding one or more first-layer candidate value(s), if necessary; calculating second-layer candidate values according to all the above-mentioned first-layer candidate values, and adding one or more second-layer candidate value(s) and its/their corresponding first-layer candidate value(s), if necessary; and calculating log likelihood ratios according to the whole first-layer and second-layer candidate values.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 13, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yao Chang, Chuan-Hu Lin, Yi-Syun Yang
  • Patent number: 9859929
    Abstract: The present invention includes a noise variance estimation circuit for wireless communication. An embodiment of the noise variance estimation circuit includes: a first estimation unit operable to generate a first estimation signal according to a reception signal and a reference signal in which the reception signal is derived from the equivalent of the reference signal; a first noise reduction unit operable to generate a first noise reduction signal by performing a first noise reduction process to the first estimation signal; a second estimation unit operable to generate a second estimation signal according to the difference between the first estimation signal and the first noise reduction signal; and a second noise reduction unit operable to execute a noise reduction adjustment according to the second estimation signal and perform a second noise reduction process to the first estimation signal in which the noise reduction adjustment affects the second noise reduction process.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: January 2, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jyun-Wei Pu, Chung-Yao Chang
  • Publication number: 20170317787
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit.
    Type: Application
    Filed: March 21, 2017
    Publication date: November 2, 2017
    Inventors: CHUNG-YAO CHANG, CHUAN-HU LIN, YI-SYUN YANG
  • Publication number: 20170317786
    Abstract: The present disclosure includes an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a search value according to a communication index and a modulation type or determine the search value according to a predetermined value, in which the communication index is related to a reception signal or a derivative thereof, the search value is associated with a search range, and a number of candidate signal value(s) in the search range is not greater than a number of all candidate signal values of the modulation type. The ML detecting circuit is configured to execute an ML calculation according to the search value and one of the reception signal and the derivative thereof, so as to calculate a log likelihood ratio of every candidate signal value in the search range.
    Type: Application
    Filed: March 21, 2017
    Publication date: November 2, 2017
    Inventors: CHUNG-YAO CHANG, WEI-CHIEH HUANG, YI-SYUN YANG
  • Publication number: 20170317788
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first-layer search value. The ML detecting circuit is configured to carry out the following steps: selecting first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, and adding one or more first-layer candidate value(s), if necessary; calculating second-layer candidate values according to all the above-mentioned first-layer candidate values, and adding one or more second-layer candidate value(s) and its/their corresponding first-layer candidate value(s), if necessary; and calculating log likelihood ratios according to the whole first-layer and second-layer candidate values.
    Type: Application
    Filed: March 21, 2017
    Publication date: November 2, 2017
    Inventors: CHUNG-YAO CHANG, CHUAN-HU LIN, YI-SYUN YANG
  • Publication number: 20170272980
    Abstract: This invention discloses a method for controlling a wireless communication device to transmit data packets. The method includes steps of: transmitting data packets; counting retry times of data packets in a predetermined time period and generating a result accordingly; comparing said result with a predetermined value and generating a comparison result accordingly; and reducing transmission time of data packets according to said comparison result.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 21, 2017
    Inventors: YU-NAN LIN, WEI-CHI LAI, SHEN-CHUNG LEE, CHUNG-YAO CHANG, WEI-HSUAN CHANG
  • Patent number: 9749171
    Abstract: A communication receiving end for receiving an inputted signal includes a signal amplifier for adjusting the inputted signal according to a first predetermined gain or a second predetermined gain to generate a first adjusted signal; an analog-to-digital converter (ADC), coupled to the signal amplifier, for converting the first adjusted signal; and a control unit, coupled to the ADC, for determining whether the ADC is saturated or not according to an output of the ADC. The first predetermined gain is associated with a first inputted signal power processed by the communication receiving end and a quantization noise of the ADC. The second predetermined gain is associated with a second inputted signal power processed by the communication receiving end and a full scale level of the ADC. The first inputted signal power is smaller than the second inputted signal power.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: August 29, 2017
    Assignee: REALTEK SEMICONDUCTOR COTPORATION
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Publication number: 20170243813
    Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Inventors: Jun-Chieh WU, Yu-Hsiang CHAO, Chung-Yao CHANG, Chun-Cheng KUO