Patents by Inventor Chung Yeh

Chung Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971824
    Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 30, 2024
    Assignee: AETHERAI IP HOLDING LLC
    Inventors: Chi-Chung Chen, Wei-Hsiang Yu, Chao-Yuan Yeh
  • Patent number: 11951091
    Abstract: Disclosed herein is a complex, a contrast agent and the method for treating a disease related to CXCR4 receptor. The complex is configured to bind the CXCR4 receptor, and is used as a medicament for diagnosis and treatment of cancers and other indications related to the CXCR4 receptor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 9, 2024
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C
    Inventors: Chien-Chung Hsia, Chung-Hsin Yeh, Cheng-Liang Peng, Chun-Tang Chen
  • Patent number: 11955401
    Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Publication number: 20240108793
    Abstract: An embodiment includes a process for treating an abdominal aortic aneurysm (AAA) endoleak with a shape memory polymer (SMP) foam device. First, a bifurcated stent graft is placed within the aneurysm while a micro guidewire is positioned within the aneurysm for future catheter access. Second, after placing the iliac graft extension, a catheter is introduced over wire to deliver embolic foams. Third, embolic foams expand and conform to the aneurysm wall. Fourth, embolic foams create a stable thrombus to prevent endoleak formation by isolating peripheral vessels from the aneurysm volume.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 4, 2024
    Inventors: Duncan J. Maitland, Todd L. Landsman, John Horn, Landon Nash, Chung Yeh
  • Publication number: 20240105098
    Abstract: A display device including a display panel is disclosed. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple pixel structures, a first gate driving circuit, and a second gate driving circuit. The pixel structures are electrically connected to the scan lines and the data lines. Multiple first output stage circuits of the first gate driving circuit disposed in a peripheral area are electrically connected to the scan lines. Multiple second output stage circuits of the second gate driving circuit disposed in the peripheral area are electrically connected to the scan lines. A channel width of a first output transistor of the first output stage circuit is greater than a channel width of a second output transistor of the second output stage circuit.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 28, 2024
    Applicant: HannStar Display Corporation
    Inventors: Jing-Xuan Chen, Yen-Chung Chen, Mu-Kai Kang, Qi-En Luo, Cheng-Yen Yeh
  • Publication number: 20240104019
    Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 28, 2024
    Applicant: AETHERAI IP HOLDING LLC
    Inventors: Chi-Chung CHEN, Wei-Hsiang YU, Chao-Yuan YEH
  • Publication number: 20240096811
    Abstract: The present disclosure provides a package structure and a method of manufacturing a package. The package structure includes a semiconductor die laterally encapsulated by an encapsulant, a redistribution structure and bumps. The redistribution structure is disposed on the semiconductor die and the encapsulant, and is electrically connected with the at least one semiconductor die. The bumps are disposed on the redistribution structure. The redistribution structure includes dielectric layers and metallic pattern layers sandwiched between the dielectric layers. The redistribution structure includes metallic pads on an outermost dielectric layer of the dielectric layers, and the outmost dielectric layer has undercut cavities beside the metallic pads.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chung Lu, Bo-Tao Chen, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Publication number: 20240095434
    Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 21, 2024
    Inventors: ZHE-WEI JIANG, JERRY CHANG JUI KAO, SUNG-YEN YEH, LI CHUNG HSU
  • Patent number: 11935833
    Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin
  • Patent number: 11923359
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shu Wu, Shu-Uei Jang, Wei-Yeh Tang, Ryan Chia-Jen Chen, An-Chyi Wei
  • Publication number: 20240071849
    Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240021475
    Abstract: A semiconductor structure includes a substrate, several gate structures formed in the substrate, dielectric portions formed on the respective gate structures, spacers adjacent to and extending along the sidewalls of the dielectric portions, source regions formed between the substrate and the spacers, and contact plugs formed between adjacent gate structures and contact the respective source regions. The source regions are adjacent to the gate structures. The sidewalls of the spacers are aligned with the sidewalls of the underlying source regions.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Hsiang LIAO, Sheng-Wei FU, Chung-Yeh LEE
  • Publication number: 20230420529
    Abstract: A semiconductor device includes a substrate, a body region on the substrate, a source region on the body region, a first trench electrode passing through the source region, the body region and a portion of the substrate, a first dielectric cap layer, a first dielectric liner and a conductive layer. The first dielectric cap layer includes a first dielectric portion directly above the first trench electrode and first dielectric spacers on two opposite sides of the first dielectric portion. The first dielectric liner surrounds the first trench electrode and the first dielectric portion. The conductive layer covers the first dielectric cap layer and includes an electrode contact. The electrode contact includes a first portion in the body region and a second portion adjacent to one of the first dielectric spacers, where the first and second portions have the same width.
    Type: Application
    Filed: June 26, 2022
    Publication date: December 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Hsiang Liao, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 11839702
    Abstract: An embodiment includes a process for treating an abdominal aortic aneurysm (AAA) endoleak with a shape memory polymer (SMP) foam device. First, a bifurcated stent graft is placed within the aneurysm while a micro guidewire is positioned within the aneurysm for future catheter access. Second, after placing the iliac graft extension, a catheter is introduced over wire to deliver embolic foams. Third, embolic foams expand and conform to the aneurysm wall. Fourth, embolic foams create a stable thrombus to prevent endoleak formation by isolating peripheral vessels from the aneurysm volume.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: December 12, 2023
    Assignees: The Texas A&M University System, SHAPE MEMORY MEDICAL, INC.
    Inventors: Duncan J. Maitland, Todd L Landsman, John Horn, Landon Nash, Chung Yeh
  • Publication number: 20230344359
    Abstract: An AC-to-DC power supply converts an input power source into an output power source, capable of having a single stage to achieve PFC and output regulation at the same time. The AC-to-DC power supply has an inductive device, a main switch, a backup circuit providing a backup power, and a power controller. The power controller controls the main switch and the backup circuit to generate a power transfer cycle with an input slot, an internal-burst slot, and a demagnetization time. During the input slot, the power controller turns ON the main switch, so the input power source supplies power to increase electromagnetic energy of the inductive device. During the internal-burst slot, the backup power supplies power to the inductive device. During the demagnetization time, the electromagnetic energy releases to supply power to the output power source or the backup power.
    Type: Application
    Filed: March 14, 2023
    Publication date: October 26, 2023
    Inventor: Wen-Chung YEH
  • Patent number: 11774729
    Abstract: A wide-angle lens assembly includes a first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth lenses. The first and second lenses are with negative refractive power and include a convex surface facing an object side and a concave surface facing an image side respectively. The third lens is a biconcave lens with negative refractive power. The fourth and fifth lenses are biconvex lenses with positive refractive power. The sixth lens is with positive refractive power and includes a convex surface facing the image side. The seventh lens is with negative refractive power and includes a concave surface facing the object side. The eighth lens is with positive refractive power and includes a convex surface facing the object side. The ninth lens is with positive refractive power and includes a concave surface facing the object side and a convex surface facing the image side.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: October 3, 2023
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventor: Ching-Chung Yeh
  • Publication number: 20230293182
    Abstract: Embodiments include, for example, mechanical release systems for implantable medical devices.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Le Le, Rose Y. Leo, Chung Yeh, Kasey Kwong, Rochelle Marlangaue, Todd L. Landsman, Michael Barrett
  • Patent number: 11747932
    Abstract: The present invention relates to a touch detecting circuit, which comprises a touch driving circuit and a touch sensing circuit. The touch driving circuit generates a touch driving signal and provides it to at least one common electrode of a panel. The touch sensing circuit receives a plurality of sensing signals via a plurality of source lines or/and a plurality of gate lines of the panel for detecting the touch location. The sensing signals are generated corresponding to the touch driving signal. In addition, the touch driving circuit may provide the touch driving signal to the source lines. The touch sensing circuit receives the sensing signals via the gate lines for detecting the touch location.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Sitronix Technology Corp
    Inventor: Cheng-Chung Yeh
  • Patent number: 11701123
    Abstract: Embodiments include, for example, mechanical release systems for implantable medical devices.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: July 18, 2023
    Assignee: SHAPE MEMORY MEDICAL, INC.
    Inventors: Le Le, Rose Y. Leo, Chung Yeh, Kasey Kwong, Rochelle Marlangaue, Todd L. Landsman, Michael Barrett
  • Patent number: 11641166
    Abstract: A rectifier circuit has a cathode node, an anode node, a rectifier switch, an auxiliary switch, an operating power capacitor and a rectifier controller supplied with power by the operating power capacitor. The rectifier switch is electrically connected to the auxiliary switch. When the rectifier controller turns OFF both the rectifier and auxiliary switches, the rectifier circuit supports a first loop, directing a first current to flow into the rectifier circuit from the anode node, through the operating power capacitor, and away the rectifier circuit from the cathode, so the operating power capacitor is charged. When the rectifier controller turns ON both the rectifier and auxiliary switches, the rectifier circuit supports a second loop directing a second current to flow into the rectifier circuit from the anode node, through the rectifier switch, and away the rectifier circuit from the cathode, without charging the operating power capacitor.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: May 2, 2023
    Inventor: Wen-Chung Yeh