Patents by Inventor Chung Yeh

Chung Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12251500
    Abstract: An embodiment includes a process for treating an abdominal aortic aneurysm (AAA) endoleak with a shape memory polymer (SMP) foam device. First, a bifurcated stent graft is placed within the aneurysm while a micro guidewire is positioned within the aneurysm for future catheter access. Second, after placing the iliac graft extension, a catheter is introduced over wire to deliver embolic foams. Third, embolic foams expand and conform to the aneurysm wall. Fourth, embolic foams create a stable thrombus to prevent endoleak formation by isolating peripheral vessels from the aneurysm volume.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: March 18, 2025
    Assignees: THE TEXAS A&M UNIVERSITY SYSTEM, SHAPE MEMORY MEDICAL, INC
    Inventors: Duncan J. Maitland, Todd L. Landsman, John Horn, Landon Nash, Chung Yeh
  • Publication number: 20250086371
    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Inventors: Li-Chung HSU, Yen-Pin CHEN, Sung-Yen YEH, Jerry Chang-Jui KAO, Chung-Hsing WANG
  • Patent number: 12241740
    Abstract: Systems, apparatuses, and methods for improved reconfigurable optical sensing are provided. For instance, an example optical sensing apparatus can include a photodetector array including a plurality of photodetectors. The optical sensing apparatus can include circuitry or one or more processing devices configured to receive one or more electrical signals representing an optical signal received by a first subset of the plurality of photodetectors; determine, based on the one or more electrical signals, a region of interest in the photodetector array for optical measurements; and deactivate, based on the region of interest, a second subset of the plurality of photodetectors of the photodetector array.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: March 4, 2025
    Assignee: ARTILUX, INC.
    Inventors: Chih-Wei Yeh, Yun-Chung Na, Tsung-Ting Wu, Shu-Lu Chen
  • Patent number: 12243821
    Abstract: A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin
  • Publication number: 20250068019
    Abstract: A display panel includes a substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and the data lines are disposed on the substrate. The pixel structure is disposed on the substrate and electrically connected to the scan lines and the data lines, and includes an active device, a pixel electrode, a capacitor electrode, an overcoat layer, a first common electrode, a second common electrode, a first passivation layer, and a second passivation layer. The active device is electrically connected one scan line, one data line, and the pixel electrode. The capacitor electrode extends from a drain and is electrically connected to the pixel electrode. The overcoat layer is disposed between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode, and is located between the overcoat layer and the capacitor electrode.
    Type: Application
    Filed: June 17, 2024
    Publication date: February 27, 2025
    Applicant: HannStar Display Corporation
    Inventors: Mu-Kai Kang, Cheng-Yen Yeh, Yen-Chung Chen, Jing-Xuan Chen, Qi-En Luo, Shao-Chien Chang
  • Publication number: 20250050558
    Abstract: An injection molding method is provided. A molding device is provided and includes a first mold, a second mold over the first mold and a mold cavity defined by the first mold and the second mold. A first mixture is injected into the mold cavity through a first feeding port. A first component is formed from the first mixture. A second mixture is injected into the mold cavity through a second feeding port. A second component is formed from the second mixture. The second component is at least partially contact with the first component, and the first component and the second component have different physical properties.
    Type: Application
    Filed: May 15, 2024
    Publication date: February 13, 2025
    Inventors: CHING-HAO CHEN, YI-CHUNG LEE, LIANG-HUI YEH
  • Patent number: 12210811
    Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.
    Type: Grant
    Filed: November 23, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Zhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20250006834
    Abstract: A semiconductor device includes a substrate having a first conductivity type and including a cell region and a termination region. A trench is disposed in the substrate and located in the cell region, and a gate electrode disposed in the trench. A shielding doped region having a second conductivity type is disposed in the substrate and directly below the trench. A buried guard ring having the second conductivity type is disposed in the substrate and located in the termination region. The buried guard ring and the shielding doped region are disposed at the same depth in the substrate. In addition, a junction termination extension structure having the second conductivity type is disposed in the substrate, located directly above and separated from the buried guard ring.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shan Lee, Chung-Yeh Lee, Fu-Hsin Chen
  • Publication number: 20240429315
    Abstract: A semiconductor device includes a trench in a substrate, a gate electrode in the trench, a source contact region on a first surface of the substrate, a drain contact region on a second surface of the substrate, a heavily doped region directly below the trench, and a current spreading layer in the substrate to surround the bottom of the trench and the heavily doped region. The heavily doped region has a first conductivity type, and the width of the heavily doped region is smaller than the width of the trench in a first direction. The current spreading layer has a second conductivity type and a gradual doping concentration that is gradually increased along the first direction from the heavily doped region to the outside of the current spreading layer.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shan Lee, Chung-Yeh Lee, Fu-Hsin Chen
  • Patent number: 12132404
    Abstract: An isolated power supplies converts an input power source in a primary side into an output power source in a secondary side, capable of transmitting a signal from the secondary side to the primary side via a transformer. The transformer has a primary winding connected with a main switch, and a secondary winding connected with a secondary-side switch. A primary-side controller controls the main switch. A secondary-side controller controls the secondary-side switch and detects a demagnetization time of the transformer. Before the end of the demagnetization time, the secondary-side controller turns OFF the secondary-side switch to signal, via the transformer, the primary-side controller, which in response turns ON the main switch to operate the isolated power supply in a continuous-conduction mode or in a boundary mode.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: October 29, 2024
    Inventor: Wen-Chung Yeh
  • Publication number: 20240266391
    Abstract: A semiconductor structure including a substrate, an epitaxy layer, an electrode structure, a first sidewall doping region, a second sidewall doping region, and a bottom doping region is provided. The substrate has a first conductivity type. The epitaxy layer has a first conductivity type and is disposed on the substrate. The electrode structure is disposed in the epitaxy layer. The electrode structure extends along a first direction. The first sidewall doping region has the first conductivity type and is disposed on one side of the electrode structure. The second sidewall doping region has a second conductivity type different than the first conductivity type and is disposed on the other side of the electrode structure. The bottom doping region has the second conductivity type and is disposed under the electrode structure. The second sidewall doping region is connected to the bottom doping region.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shan LEE, Chung-Yeh LEE, Fu-Hsin CHEN
  • Publication number: 20240182456
    Abstract: The present invention relates to compounds of formula (I) as activators of glucagon-like peptide 1 (GLP1) receptor for the treatment of obesity, type 2 diabetes mellitus, insulin resistance, hyperinsulinemia, glucose intolerance, hyperglycemia, one or more diabetic complications, diabetic nephropathy, dyslipidemia, non-alcoholic fatty liver disease (NAFLD), non-alcoholic steatohepatitis (NASH), hypertension, atherosclerosis, peripheral arterial disease, stroke, cardiomyopathy, atrial fibrillation, heart failure, coronary heart disease and neuropathy. Preferred compounds are e.g. 2-((4-((S)-2-(4-chloro-2-fluorophenyl)-2-methylbenzo[d][1,3]dioxol-4-yl)piperidin-1-yl)methyl)-1-(((S)-oxetan-2-yl)methyl)-1H-imidazole derivatives and similar compounds, such as e.g. C-1, C-2, C-3, C-4 and other compounds.
    Type: Application
    Filed: April 11, 2022
    Publication date: June 6, 2024
    Inventors: Martin ALLAN, Matthew CARSON, Thomas CAYA, Lara CZABANIUK, Ming QIAN, Daniel SMITH, Troy SMITH, Liansheng SU, Chung-Yeh WU, Lihua YANG, Chun ZHANG, Ping ZHANG, Xilin ZHOU
  • Publication number: 20240178315
    Abstract: A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer formed on the substrate, a well region extending from a top surface of the epitaxial layer into the epitaxial layer, a drift region formed in the epitaxial layer and in contact with the bottom surface of the well region, a gate structure and a conductive structure. The epitaxial layer has the first conductivity type, the well region has the second conductivity type, and the drift region has the first conductivity type. The gate structure that extends from the top surface of the epitaxial layer penetrates the well region and is in contact with the drift region. The conductive structure is formed in the drift region and disposed below the gate structure. A gate electrode of the gate structure is separated from the underlying conductive structure by the gate dielectric layer of the gate structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shan LEE, Chung-Yeh LEE, Fu-Hsin CHEN
  • Publication number: 20240178270
    Abstract: A semiconductor device includes a substrate, an epitaxial layer on the substrate, a well region in the epitaxial layer, an insulating pillar extending into the epitaxial layer, a first doping region in the epitaxial layer and surrounding the insulating pillar, a second doping region under the first doping region, and a gate structure formed at one lateral side of the insulating pillar and extending into the epitaxial layer. The substrate and the epitaxial layer each have a first conductivity type. The well region and the first and second doping regions each have a second conductivity type. The gate structure is separated from the insulating pillar. The insulating pillar penetrates the first doping region by extending from the top portion to the bottom portion of the first doping region. The first doping region is electrically connected to the well region.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shan LEE, Chung-Yeh LEE, Fu-Hsin CHEN
  • Publication number: 20240170544
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxy layer, a well region, a gate electrode, a conductive structure, and a source electrode. The substrate has a first conductive type. The epitaxy layer has the first conductive type and is disposed on the substrate. The well region has a second conductive type. The second conductive type is different than the first conductive type. The well region is disposed in the epitaxy layer. The gate electrode is disposed on the well region. The conductive structure includes an upper portion and a lower portion. The lower portion extends in the direction of the substrate into the epitaxy layer and the upper portion is disposed on the epitaxy layer. The source electrode is disposed on the conductive structure.
    Type: Application
    Filed: November 21, 2022
    Publication date: May 23, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shan LEE, Chung-Yeh LEE, Fu-Hsin CHEN
  • Publication number: 20240108793
    Abstract: An embodiment includes a process for treating an abdominal aortic aneurysm (AAA) endoleak with a shape memory polymer (SMP) foam device. First, a bifurcated stent graft is placed within the aneurysm while a micro guidewire is positioned within the aneurysm for future catheter access. Second, after placing the iliac graft extension, a catheter is introduced over wire to deliver embolic foams. Third, embolic foams expand and conform to the aneurysm wall. Fourth, embolic foams create a stable thrombus to prevent endoleak formation by isolating peripheral vessels from the aneurysm volume.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 4, 2024
    Inventors: Duncan J. Maitland, Todd L. Landsman, John Horn, Landon Nash, Chung Yeh
  • Publication number: 20240021475
    Abstract: A semiconductor structure includes a substrate, several gate structures formed in the substrate, dielectric portions formed on the respective gate structures, spacers adjacent to and extending along the sidewalls of the dielectric portions, source regions formed between the substrate and the spacers, and contact plugs formed between adjacent gate structures and contact the respective source regions. The source regions are adjacent to the gate structures. The sidewalls of the spacers are aligned with the sidewalls of the underlying source regions.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Hsiang LIAO, Sheng-Wei FU, Chung-Yeh LEE
  • Publication number: 20230420529
    Abstract: A semiconductor device includes a substrate, a body region on the substrate, a source region on the body region, a first trench electrode passing through the source region, the body region and a portion of the substrate, a first dielectric cap layer, a first dielectric liner and a conductive layer. The first dielectric cap layer includes a first dielectric portion directly above the first trench electrode and first dielectric spacers on two opposite sides of the first dielectric portion. The first dielectric liner surrounds the first trench electrode and the first dielectric portion. The conductive layer covers the first dielectric cap layer and includes an electrode contact. The electrode contact includes a first portion in the body region and a second portion adjacent to one of the first dielectric spacers, where the first and second portions have the same width.
    Type: Application
    Filed: June 26, 2022
    Publication date: December 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Hsiang Liao, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 11839702
    Abstract: An embodiment includes a process for treating an abdominal aortic aneurysm (AAA) endoleak with a shape memory polymer (SMP) foam device. First, a bifurcated stent graft is placed within the aneurysm while a micro guidewire is positioned within the aneurysm for future catheter access. Second, after placing the iliac graft extension, a catheter is introduced over wire to deliver embolic foams. Third, embolic foams expand and conform to the aneurysm wall. Fourth, embolic foams create a stable thrombus to prevent endoleak formation by isolating peripheral vessels from the aneurysm volume.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: December 12, 2023
    Assignees: The Texas A&M University System, SHAPE MEMORY MEDICAL, INC.
    Inventors: Duncan J. Maitland, Todd L Landsman, John Horn, Landon Nash, Chung Yeh
  • Publication number: 20230344359
    Abstract: An AC-to-DC power supply converts an input power source into an output power source, capable of having a single stage to achieve PFC and output regulation at the same time. The AC-to-DC power supply has an inductive device, a main switch, a backup circuit providing a backup power, and a power controller. The power controller controls the main switch and the backup circuit to generate a power transfer cycle with an input slot, an internal-burst slot, and a demagnetization time. During the input slot, the power controller turns ON the main switch, so the input power source supplies power to increase electromagnetic energy of the inductive device. During the internal-burst slot, the backup power supplies power to the inductive device. During the demagnetization time, the electromagnetic energy releases to supply power to the output power source or the backup power.
    Type: Application
    Filed: March 14, 2023
    Publication date: October 26, 2023
    Inventor: Wen-Chung YEH