Patents by Inventor Chung-Yen Lu

Chung-Yen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10810700
    Abstract: A method of adjusting texture coordinates based on control regions in a panoramic image is disclosed. The method comprises determining warping coefficients of a plurality of control regions in a panoramic image; retrieving two selected warping coefficients out of the warping coefficients for each of a plurality of camera images with respect to each vertex from a first vertex list according to two coefficient indices for each camera image in its data structure; calculating an interpolated warping coefficient for each camera image with respect to each vertex according to the two selected warping coefficients and a coefficient blending weight for each camera image in its data structure; and, calculating modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and original texture coordinates for each camera image in its data structure to form a second vertex list.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 20, 2020
    Assignee: ASPEED TECHNOLOGY INC.
    Inventor: Chung-Yen Lu
  • Publication number: 20200286206
    Abstract: A method of adjusting texture coordinates based on control regions in a panoramic image is disclosed. The method comprises determining warping coefficients of a plurality of control regions in a panoramic image; retrieving two selected warping coefficients out of the warping coefficients for each of a plurality of camera images with respect to each vertex from a first vertex list according to two coefficient indices for each camera image in its data structure; calculating an interpolated warping coefficient for each camera image with respect to each vertex according to the two selected warping coefficients and a coefficient blending weight for each camera image in its data structure; and, calculating modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and original texture coordinates for each camera image in its data structure to form a second vertex list.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventor: Chung-Yen LU
  • Publication number: 20200219230
    Abstract: A calibration method for linking spherical coordinates to texture coordinates is provided. The method comprises: installing a plurality of lamps forming a horizontal semicircle arc and a rotation equipment located at its circle center; mounting a N-lens camera on the rotation equipment; causing the N-lens camera to spin about a spin axis passing through two ends of the horizontal semicircle arc and capture a plurality of lens images for different spin angles by the rotation equipment; and, determining longitude and latitude coordinates of a plurality of calibration points according to the different spin angles and the texture coordinates of the calibration points in the lens images to create a link between the spherical coordinates and the texture coordinates. Different positions of the lamps respectively represent different latitudes and different spin angles respectively represent different longitudes. Heights of the camera and the lamps are the same.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 9, 2020
    Inventors: Chung-Yen LU, Cheng-Yi HSU, Hsin-Yu CHEN
  • Patent number: 10484688
    Abstract: A video encoding apparatus is disclosed. The apparatus is used to process a sequence of frames of video data and each frame comprises a plurality of processing blocks. The apparatus comprises a skip decision circuit and an encoder. The skip decision circuit generates a control signal according to a similarity checking result and a comparison result between a first quantization parameter for a first processing block from a current frame and a second quantization parameter for a second processing block from a previous frame. The encoder encodes the first processing block to generate an encoded bit stream and the first quantization parameter. The second processing block resides at the same location in the previous frame as the first processing block in the current frame.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 19, 2019
    Assignee: ASPEED TECHNOLOGY INC.
    Inventor: Chung-Yen Lu
  • Publication number: 20190230358
    Abstract: A video encoding apparatus is disclosed. The apparatus is used to process a sequence of frames of video data and each frame comprises a plurality of processing blocks. The apparatus comprises a skip decision circuit and an encoder. The skip decision circuit generates a control signal according to a similarity checking result and a comparison result between a first quantization parameter for a first processing block from a current frame and a second quantization parameter for a second processing block from a previous frame. The encoder encodes the first processing block to generate an encoded bit stream and the first quantization parameter. The second processing block resides at the same location in the previous frame as the first processing block in the current frame.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventor: Chung-Yen LU
  • Patent number: 10362684
    Abstract: The present invention relates to a method for improving adhesion between ceramic and a thick film circuit. The method is particularly directed to accelerate the formation of a ceramic-metal eutectic phase between the ceramic carrier and the metal circuit by solid-phase diffusion bonding under a positive atmosphere. A metallic conductive slurry or its oxide slurry is printed on the surface of the ceramic carrier to form a circuit pattern by a thick film screen printing. The ceramic carrier is placed in an oven with temperature controlled by a program under a positive-pressure atmosphere of an inert gas including nitrogen, hydrogen or their mixtures. An eutectic phase is formed between the ceramic carrier and the metal circuit under a high temperature eutectic condition to increase the adhesion between the ceramic carrier and the thick film circuit.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 23, 2019
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chia-Ting Lin, Jlin-Fuh Yau, Chung-Yen Lu, Yang-Kuo Kuo
  • Publication number: 20190172986
    Abstract: A manufacturing method of a high reflection mirror with polycrystalline aluminum nitride includes (A) providing a polycrystalline aluminum nitride substrate having a polished surface, and utilizing a magnetron sputtering apparatus to react an aluminum target and a plasma formed of nitrogen and argon for forming an aluminum nitride film on the surface of the polycrystalline aluminum nitride substrate, wherein the aluminum nitride film fills into a hole or a gap generated by a lattice defect of the surface of the polycrystalline aluminum nitride substrate; (B) thinning, grinding and polishing the aluminum nitride film for planarizing the polycrystalline aluminum nitride substrate; (C) forming an aluminum coating layer on the aluminum nitride film by a vacuum coating apparatus; (D) forming a sliver coating layer on the aluminum coating layer by another vacuum coating apparatus; and (E) forming a surface-protecting layer on the sliver coating layer.
    Type: Application
    Filed: July 12, 2018
    Publication date: June 6, 2019
    Inventors: Chung-Yen Lu, Yung-Han Huang
  • Patent number: 10186067
    Abstract: A transform apparatus applied in an image processing system with an image capture module is disclosed. The transform apparatus comprises a geometry information detector, a parameter setup unit, a primitive assembly unit and a geometry processing circuit. The geometry information detector measures geometry information of the image capture module. The parameter setup unit calculates geometry parameters and determines whether to assert an enable signal according to the geometry information. The primitive assembly unit receives an original vertex list and the enable signal to generate a vertex/ID flow. The geometry processing circuit receives the geometry parameters and performs geometry transform operations over the vertex/ID flow in response to whether the first enable signal is asserted to generate a modified vertex list. The geometry information comprises at least one of a displacement and rotation angles of the image capture module.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 22, 2019
    Assignee: ASPEED TECHNOLOGY INC.
    Inventors: Chung-Yen Lu, Pei-Hen Hung, Jing-Chuan Chen
  • Patent number: 10110931
    Abstract: A variable length coder is disclosed. The variable length coder comprises a size determining unit and a first residual coder. The size determining unit determines a maximum size based on sizes of quantized residuals in a current group and determines whether to enable the first residual coder according to the maximum size. When the maximum size is equal to 1, the first residual coder is enabled to encode the quantized residuals as one symbol to generate a first encoded suffix according to a variable length coding scheme.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 23, 2018
    Assignee: ASPEED TECHNOLOGY INC.
    Inventor: Chung-Yen Lu
  • Patent number: 10104288
    Abstract: A vertex processing device applied in an image processing system having an image capture module is disclosed. The image capture module generates camera images. The vertex processing device comprises a coefficient interpolation unit and a coordinate modifying unit. The coefficient interpolation unit generates an interpolated warping coefficient for each camera image with respect to each vertex from a vertex list based on n number of warping coefficients and its original texture coordinates in each camera image. The coordinate modifying unit calculates modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and its original texture coordinates in each camera image. The vertex list comprises vertices with data structures that define vertex mapping between the camera images and a panoramic image. The n number of warping coefficients correspond to n number of overlap regions in the panoramic image.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 16, 2018
    Assignee: ASPEED TECHNOLOGY INC.
    Inventors: Pei-Hen Hung, Chung-Yen Lu, Kuo-Wei Yeh, Jing-Chuan Chen
  • Publication number: 20180227484
    Abstract: A vertex processing device applied in an image processing system having an image capture module is disclosed. The image capture module generates camera images. The vertex processing device comprises a coefficient interpolation unit and a coordinate modifying unit. The coefficient interpolation unit generates an interpolated warping coefficient for each camera image with respect to each vertex from a vertex list based on n number of warping coefficients and its original texture coordinates in each camera image. The coordinate modifying unit calculates modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and its original texture coordinates in each camera image. The vertex list comprises vertices with data structures that define vertex mapping between the camera images and a panoramic image. The n number of warping coefficients correspond to n number of overlap regions in the panoramic image.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Pei-Hen HUNG, Chung-Yen LU, KUO-WEI YEH, Jing-Chuan CHEN
  • Publication number: 20180114348
    Abstract: A transform apparatus applied in an image processing system with an image capture module is disclosed. The transform apparatus comprises a geometry information detector, a parameter setup unit, a primitive assembly unit and a geometry processing circuit. The geometry information detector measures geometry information of the image capture module. The parameter setup unit calculates geometry parameters and determines whether to assert an enable signal according to the geometry information. The primitive assembly unit receives an original vertex list and the enable signal to generate a vertex/ID flow. The geometry processing circuit receives the geometry parameters and performs geometry transform operations over the vertex/ID flow in response to whether the first enable signal is asserted to generate a modified vertex list. The geometry information comprises at least one of a displacement and rotation angles of the image capture module.
    Type: Application
    Filed: October 25, 2016
    Publication date: April 26, 2018
    Inventors: Chung-Yen LU, Pei-Hen HUNG, Jing-Chuan CHEN
  • Publication number: 20180018807
    Abstract: An image processing apparatus is disclosed, which comprises a rasterization engine, a texture mapping module and a destination buffer. The rasterization engine receives a group of vertices from a vertex list and performs polygon rasterization operations for a point within the group of vertices forming a polygon to generate texture coordinates for each camera image. The vertex list comprises a plurality of vertices with their data structures. The texture mapping module texture maps texture data from each camera image according to its texture coordinates to generate a sample value for each camera image. The destination buffer is coupled to the texture mapping module and stores the panoramic image. Here, the data structures define a mapping between the panoramic image and the camera images.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 18, 2018
    Inventors: Chung-Yen LU, Pei-Hen HUNG, HUNG-JU HUANG, HUNG-MING LIN
  • Patent number: 9857865
    Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 2, 2018
    Assignee: Aspeed Technology Inc.
    Inventors: Chung-Yen Lu, Hung-Ming Lin
  • Patent number: 9814143
    Abstract: A method of forming a pattern with high aspect ratio on a polycrystalline aluminum nitride substrate comprises the steps of (A) providing an aluminum nitride substrate and forming a barrier layer on the aluminum nitride substrate; (B) etching the barrier layer with an energy beam to form at least one recess in the barrier layer; (C) plasma etching the substrate to deepen the recess into the aluminum nitride substrate; (D) removing the barrier layer to obtain the aluminum nitride substrate having at least one pattern with high aspect ratio. The method uses the energy beam to directly form a pattern on the barrier layer, and further employs plasma etching to prepare the aluminum nitride substrate having a pattern with high aspect ratio quickly and effectively.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 7, 2017
    Assignee: National Chung Shan Institute of Science and Technology
    Inventors: Chung-Yen Lu, Yi-Hsiuan Yu, Chia-Ting Lin, Lea-Hwung Leu
  • Publication number: 20170318314
    Abstract: A variable length coder is disclosed. The variable length coder comprises a size determining unit and a first residual coder. The size determining unit determines a maximum size based on sizes of quantized residuals in a current group and determines whether to enable the first residual coder according to the maximum size. When the maximum size is equal to 1, the first residual coder is enabled to encode the quantized residuals as one symbol to generate a first encoded suffix according to a variable length coding scheme.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 2, 2017
    Inventor: Chung-Yen LU
  • Publication number: 20170168550
    Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventors: Chung-Yen LU, Hung-Ming LIN
  • Patent number: 9641907
    Abstract: An image transmission system with finite re-transmission function is disclosed. The system of the invention comprises a communication channel, a transmitting device and a receiving device. The transmitting device comprises an encoder, a first coded buffer and a transmitter. The receiving device comprises a receiver, a second coded buffer, a decoder, a decoded buffer and a display control unit. The system of the invention uses line buffers due to its line-based encoding/decoding scheme, to thereby reduce hardware cost. In addition, the image transmission system of the invention conducts a skip-line-encoding mechanism, a stop-retransmitting mechanism and a line-ID-control mechanism, to thereby achieve a real-time transmission/display.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 2, 2017
    Assignee: ASPEED TECHNOLOGY INC.
    Inventor: Chung-Yen Lu
  • Patent number: 9558086
    Abstract: A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 31, 2017
    Assignee: ASPEED TECHNOLOGY INC.
    Inventors: Hung-Ju Huang, Fu-Chou Hsu, Chung-Yen Lu
  • Patent number: 9531915
    Abstract: An image encoding system is disclosed. The image encoding system comprises a wavelet transform unit and a processing circuit. The wavelet transform unit performs a multiple-line-based wavelet transform on plural consecutive component lines to generate a wavelet transformed image comprising wavelet coefficients of plural sub-bands. The processing circuit coupled to the wavelet transform unit for quantizing, scanning and encoding the wavelet coefficients to generate a compressed image. Here, a number of the plural consecutive component lines is a multiple of 2 and less than 5. Since the wavelet transform unit performs the multiple-line-based wavelet transform to reduce the storage amount and maintain a good compression quality, an image encoding system of the invention can use SRAM buffers instead of a DRAM buffer.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 27, 2016
    Assignee: ASPEED TECHNOLOGY INC.
    Inventor: Chung-Yen Lu