Abstract: An edge-oriented interpolation method for deinterlacing with sub-pixel accuracy. To interpolate a missing pixel of a first scan line, first, a first pixel group of a second scan line and a second pixel group of a third scan line in a first orientation are provided, and a third pixel group of the second scan line and a fourth pixel group of the third scan line in a second orientation are provided. Then, a first sub-pixel of the second scan line is calculated according to the first pixel group and the third pixel group, and a second sub-pixel of the third scan line is calculated according to the second pixel group and the fourth pixel group by employing a linear interpolation method or an ideal interpolation function based on the sampling theorem. Thereafter, the missing pixel is interpolated according to the first sub-pixel and the second sub-pixel.

Abstract: A color processing method enhances color intensity and saturation in RGB domain. For a pixel to be enhanced, a new set of color values, (R′,G′,B′), are computed base on its original color values, (R,G,B). The original red, green, and blue intensity values are used to obtain a scaling factor and an intensity base. The scaling factor is then compared with a user controlled scaling factor to obtain a final scaling factor. The new set of color values are computed based on the final scaling factor and the intensity base to enhance the intensity and saturation of the pixel.

Abstract: A method for converting N-bit image data of a digital image into M-bit image data, in which N−M=K, K>0, is disclosed. The method is adapted to be used for dithering in an image processing system or a computer graphic system. For example, an N-bit red color value of each pixel of the digital image can be converted into an M-bit red color value by this method with little or no color deviation. According to the method, a difference of the most significant n bits and the least significant n bits of the N-bit image data of a pixel is used as a preliminary criterion for color value conversion, in which n is preferably equal to K. An apparatus for converting N-bit image data of a digital image into M-bit image data, in which N−M=K, K>0, is also disclosed. The apparatus includes a subtraction operator for realizing the difference of the most significant n bits and the least significant n bits of the N-bit image data of the pixel.

Abstract: An apparatus for line drawing using a plurality of pixels to display a line, including a first parameter generating module, a second parameter generating module, a storage module, a retrieving module, and a calculating module. In this case, the first parameter generating module generates a first parameter according to a slope of the line. The second parameter generating module generates a second parameter according to the distance between one of the pixels and the line in axial directions. The storage module stores an index table, which records at least a blending factor and the correlations between the first parameter, second parameter, and blending factor. Therefore, the retrieving module searches for the blending factor from the index table according to the first and second parameter. Finally, the calculating module determines the color of this pixel according to the blending factor.

Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (−1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2−K)+(Bx·2−N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1≦Mx<2, fx is a N-bit fraction, Ax is a value of the most significant K bits of fx, Bx is a value of the least significant (N−K) bits of fx, 0≦K<N, and p, K, N are natural numbers. The apparatus includes: a first multiplier, a logarithmic table, a first adder, a divider, a Taylor-Series approximation circuit, a second multiplier, and a second adder.

Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein N=N1+N2+ . . . +NK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent.

Abstract: An apparatus for controlling a stereo video display with non-stereo video source includes a memory, a read/write controller and a motion analyzer. The memory stores a current frame, a previous frame of the current frame, and a next frame for the current frame that is in preparation. The current frame and the previous frame are for a dextral image and a sinistral image of a stereoscopic image respectively. The read/write controller controls the addresses to write the current frame and the next frame into the memory, and the reading order of the current frame and the previous frame.

Abstract: An apparatus for reusing lighted vertex data in a computer graphics system. The disclosed apparatus includes a storage area having entries that are employed to store lighted vertex indices. The apparatus has a number of comparators each of which compares respective content of the corresponding entry with a presently received vertex index to determine whether they are the same. It also includes an encoder, a counter and a multiplexer. In response to output of the comparators, the encoder reports a hit value and produces an address dedicated to the entry storing the lighted vertex index that is the same as the received vertex index. The counter increases an update pointer by one when the hit value is not indicative of a hit status. Based on the hit value, the multiplexer selectively outputs the address or the update pointer as a reference position.

Abstract: A fast line drawing method. First, the coordinates of two end points are received and a current point is assigned to one of the end points. The differences of x and y coordinates (&Dgr;x and &Dgr;y) and the sum of error E are computed, the integer part of &Dgr;x over &Dgr;y is denoted as Q. The current point is checked to determine whether it has reached the end point. If not and the value of E is negative, a point at the current point is drawn. The y-coordinate of the current point and E are updated by (Y+1) and (E−2&Dgr;x) respectively if E is non-negative, a span of pixels from (X,Y) to (X+Q-1,Y) are drawn if the coordinate of last of Q points is less than the end point. Otherwise, a span of pixels from (X,Y) to (x2,Y) are drawn.

Abstract: A culling method and module is provided to generate a culling decision for efficient culling a back-face triangle of a 3D graphics. The culling module includes a comparison circuit and a culling decision circuit. The comparison circuit compares the coordinates of three vertices of each triangle and then outputs the comparison results to the culling decision circuit. The culling decision circuit then generates a decision result by looking up a predetermined lookup table according to the comparison results and a pre-determined coordinate orientation signal.

Abstract: A setup/shading device for performing a shading process in respect to a plurality of triangles. It includes a shading coordinate generator, a common term setup unit and a plurality of attribute setup/shading units. The shading coordinate generator produces coordinates of the pixels contained in a current triangle. The common term setup unit is used to determine common term data contained in the coefficients of the plane equations. The attribute setup/shading units each include first and second hardware circuits and are operated in a first mode or a second mode. In the first mode, the two hardware circuits cooperate to calculate the attribute values of the pixels by absolute shading. In the second mode, the second hardware circuit calculates the attribute values of the pixels by relative shading and the first hardware circuit calculates the coefficients of the plane equation corresponding to a next triangle subsequent to the current triangle.

Abstract: A vertex data access apparatus and method. The apparatus receives a vertex index, compares the vertex index with any vertices' indices used before, issues a request if necessary for fetching vertex data in system memory, stores the return vertex data in a vertex data queue and gets corresponding vertex data from the vertex data queue for further processing and, more particularly, if the vertex index is the same as one of those vertices' indices, the corresponding vertex data can be directly fetched from the vertex data queue. The vertex data queue performs the vertex cache function.

Abstract: An apparatus and method for reducing clipping computations needed to perform clipping of an input primitive in a clipping machine of a computer graphics system. The present invention provides an intersection cache storing the previous clipped vertex data for reuse in the following operations, thus dramatically reducing the amount of data calculation. The method includes providing a plane identification designated to a clipping plane and a pair of vertex indices designated to an edge of the graphics primitive, comparing the plane identification and the pair of vertex indices with a cached plane identification and a pair of cached vertex indices, determining a result from the comparing step, and retrieving cached vertex data as clipped vertex data defining a clipped primitive if the result is indicative of a cache hit status.

Abstract: An apparatus and method for pixel color enhancement are provided. The preferred embodiment includes a first circuitry, a second circuitry, a third circuitry, a fourth circuitry. In a preferred embodiment, the apparatus further includes a fifth circuitry. The first circuitry determines and outputs a reference value X. The second circuitry inputs the X, and (R, G, B) and subtracts X from three components (R, G, B) respectively to obtain values of (R−X), (G−X) and (B−X). The third circuitry inputs values of (R−X), (G−X) and (B−X) and scale values of (R−X), (G−X) and (B−X) by a factor S to generate values of S*(R−X), S*(G−X) and S*(B−X). The fourth circuitry 16 respectively adds values of S*(R−X), S*(G−X) and S*(B−X) to three components (R, G, B) to generate three enhanced components (R′, G′, B′).

Abstract: A method for converting N-bit image data of a digital image into M-bit image data, in which N−M=K, K>0, is disclosed. The method is adapted to be used for dithering in an image processing system or a computer graphic system. For example, an N-bit red color value of each pixel of the digital image can be converted into an M-bit red color value by this method with little or no color deviation. According to the method, a difference of the most significant n bits and the least significant n bits of the N-bit image data of a pixel is used as a preliminary criterion for color value conversion, in which n is preferably equal to K. An apparatus for converting N-bit image data of a digital image into M-bit image data, in which N−M=K, K>0, is also disclosed. The apparatus includes a subtraction operator for realizing the difference of the most significant n bits and the least significant n bits of the N-bit image data of the pixel.

Abstract: The present invention is to provide a culling method, used in the computer graphics systems, for determining the visibility of two adjacent polygons of a polyhedron at the same time. It also provides a culling apparatus, which uses the method to execute the culling test. The culling apparatus comprises one multiplier, three multiplexers, two registers, one adder/subtractor, and a controller with a set of instructions to control the whole procedure.

Abstract: The present invention discloses a method for accelerated triangle occlusion culling in the computer graphic system. The triangle-based visibility testing is determined by using a triangle within a particular group of Coarse-Z buffer. If the triangle within a particular group of Coarse-Z buffer is hidden, then the triangle will be discarded. By using triangle-based visibility pre- test determined by the Coarse-Z buffer, the graphics system can skip hidden surface at a great lick and the requirement of memory bandwidth and unnecessary computations is eliminated.

Abstract: A graphics system minimizes the idle time of a host processor while sending a large amount of graphics instructions in a graphics system. The graphics system includes a host processor, a system memory, a graphics memory and a graphics accelerating device (GAD) that interconnects the host processor and the graphics memory. The host processor divides the graphics instructions into graphics commands and graphics data and temporarily stores the graphics data in the system memory. The GAD receives the graphics commands coming from the host processor and receives the graphics data coming from the system memory, respectively, and sends the processed outcome to the graphics memory. Due to the graphics data being temporarily stored in the system memory, the host processor will not be idle even though many consecutive 3D graphics instructions are sent from the host processor to the GAD.

Abstract: An apparatus and method for pixel block compression during rendering in computer graphics is proposed. The method is to divide the image frame into a plurality of blocks and compute those blocks covered by a rendering triangle. If a block is not totally covered by the triangle, the method will read in and decompress the block for reference. Then, the system will render the blocks covered by the triangle and compress each block. At last, the system stores the compressed data stream into memory. The compression method is first to compute a plurality of initial seed colors for clustering the block of pixels. Then, each pixel within the block will be classified into groups with the corresponding initial seed colors. Those pixels with the same initial seed color are averaged to become a new final seed color. Therefore, the coded data comprise the index table and the final seed colors.

Abstract: The present invention is to provide a culling method, used in the computer graphics systems, for determining the visibility of two adjacent polygons of a polyhedron at the same time. It also provides a culling apparatus, which uses the method to execute the culling test. The culling apparatus comprises one multiplier, three multiplexers, two registers, one adder/subtractor, and a controller with a set of instructions to control the whole procedure.