Abstract: A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.

Abstract: An embodiment of a graphic remoting system of the present invention includes a network, a server and a client device. The network is applied to a RDP protocol. The server transfers display rendering commands which indicates a destination region through the network. The client device receives the display rendering commands. The client device of the present invention includes at least a graphic render engine, at least a surface, at least a mask generator, a plurality of mask buffer, at least a direct memory access with masks, and a plurality of display buffers. The surface is used for storing an image. The graphic render engine generates the image and stores the image into the surface according to the destination region. The mask buffers is used for storing bit masks; wherein the content values of the mask buffers are indicating updated areas of the image stored in the surface. The mask generator generates the bit masks according to the destination region, and stores the bit masks into the mask buffers.

Abstract: A signal processor of the invention includes a host processor, a command queue, a graphics decoding circuit, a video decoding circuit, a composition engine and two display buffers. The host processor generates graphics commands and sets a video flag to active based on graphics encoded data, video encoded data and mask encoded data from a network. The command queue asserts a control signal according to the graphics commands. The graphics decoding circuit generates the graphics frame and two surface mask while the video decoding circuit generates the video frame and a video mask. The composition engine transfers the graphics frame, the video frame or a content of one of two display buffers to the other display buffer according to the video mask and the two surface masks when the control signal is asserted or when the video flag is active.

Abstract: A signal processor of the invention includes a host processor, a command queue, a graphics decoding circuit, a video decoding circuit, a composition engine and two display buffers. The host processor generates graphics commands and sets a video flag to active based on graphics encoded data, video encoded data and mask encoded data from a network. The command queue asserts a control signal according to the graphics commands. The graphics decoding circuit generates the graphics frame and two surface mask while the video decoding circuit generates the video frame and a video mask. The composition engine transfers the graphics frame, the video frame or a content of one of two display buffers to the other display buffer according to the video mask and the two surface masks when the control signal is asserted or when the video flag is active.

Abstract: An embodiment of a graphic remoting system of the present invention includes a network, a server and a client device. The network is applied to a RDP protocol. The server transfers display rendering commands which indicates a destination region through the network. The client device receives the display rendering commands. The client device of the present invention includes at least a graphic render engine, at least a surface, at least a mask generator, a plurality of mask buffer, at least a direct memory access with masks, and a plurality of display buffers. The surface is used for storing an image. The graphic render engine generates the image and stores the image into the surface according to the destination region. The mask buffers is used for storing bit masks; wherein the content values of the mask buffers are indicating updated areas of the image stored in the surface. The mask generator generates the bit masks according to the destination region, and stores the bit masks into the mask buffers.

Abstract: A method and apparatus for displaying images is disclosed. The method of the invention includes the steps of: transferring a content of a first one of the display buffers to the display device; overwriting a second one of the display buffers with first image data, wherein the first image data represent data of updated pixels between two corresponding adjacent frames; obtaining a bit-map mask according to the updated pixels, wherein the bit-map mask indicates altered pixels for the two corresponding adjacent frames; and, then overwriting the second one of the display buffers with second image data from the other display buffers according to at least one bit-map mask.

Abstract: A method of accessing a desired memory location applied in a cipher processing apparatus is disclosed. The cipher processing apparatus comprises a plurality of registers and a register storage. The method comprises the steps of: reading a cipher instruction comprising an opcode field and an operand specifier field; reading a base address from one of the plurality of registers according to a register-id sub-field; respectively reading a bit length and an index value from the register storage and an index sub-field; determining the desired memory location according to the base address, the bit length and the index value; and, accessing the desired memory location to obtain a desired field variable. Here, the operand specifier field comprises the register-id sub-field and the index sub-field.

Abstract: An image transmission system with finite re-transmission function is disclosed. The system of the invention comprises a communication channel, a transmitting device and a receiving device. The transmitting device comprises an encoder, a first coded buffer and a transmitter. The receiving device comprises a receiver, a second coded buffer, a decoder, a decoded buffer and a display control unit. The system of the invention uses line buffers due to its line-based encoding/decoding scheme, to thereby reduce hardware cost. In addition, the image transmission system of the invention conducts a skip-line-encoding mechanism, a stop-retransmitting mechanism and a line-ID-control mechanism, to thereby achieve a real-time transmission/display.

Abstract: An image encoding system is disclosed. The image encoding system comprises a wavelet transform unit and a processing circuit. The wavelet transform unit performs a multiple-line-based wavelet transform on plural consecutive component lines to generate a wavelet transformed image comprising wavelet coefficients of plural sub-bands. The processing circuit coupled to the wavelet transform unit for quantizing, scanning and encoding the wavelet coefficients to generate a compressed image. Here, a number of the plural consecutive component lines is a multiple of 2 and less than 5. Since the wavelet transform unit performs the multiple-line-based wavelet transform to reduce the storage amount and maintain a good compression quality, an image encoding system of the invention can use SRAM buffers instead of a DRAM buffer.

Abstract: A baseboard management system suitable for use in a high density server system is provided. The baseboard management system comprises: a plurality of baseboard management controller (BMC) node respectively located on the servers; and, a main BMC coupled to a network and to the BMC nodes through a communication link for executing a management software; wherein each BMC node is connected with a corresponding host processor and with server board peripherals individually on a corresponding server; and wherein the main BMC in cooperation with the BMC nodes is used to manage the servers remotely.

Abstract: An auto firmware update device and method for fault-tolerance is provided. According to an embodiment of the invention, the auto firmware update device includes a serial port, a processor, a timer, a memory and a control unit. The serial port is used for coupling to an external device and updating firmware. The processor fetches instructions to boot. The timer is configured to start counting when the processor boots or restart each time, wherein the timer generates an alarm signal if the timer expires before the processor successfully boots. The memory stores a copy of firmware for booting. The control unit receives the alarm signal to stop the processor, downloads another copy of firmware for booting through the serial port to write to the memory, and restarts the processor.

Abstract: A method and apparatus for displaying images is disclosed. The method of the invention includes the steps of: transferring a content of a first one of the display buffers to the display device; overwriting a second one of the display buffers with first image data, wherein the first image data represent data of updated pixels between two corresponding adjacent frames; obtaining a bit-map mask according to the updated pixels, wherein the bit-map mask indicates altered pixels for the two corresponding adjacent frames; and, then overwriting the second one of the display buffers with second image data from the other display buffers according to at least one bit-map mask.

Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

Abstract: A video/image processing apparatus includes a storage module, a motion estimation module, and a plurality of video/image processing blocks. The storage module is arranged for storing a plurality of images. The motion estimation module is coupled to the storage module, and arranged for retrieving the images from the storage module, and generating motion vectors according to the images. The video/image processing blocks are coupled to the motion estimation module, and arranged for performing a plurality of different video/image processing operations, respectively, wherein each of the video/image processing blocks receives the motion vectors generated from the motion estimation module, and refers to the received motion vectors to perform a designated video/image processing operation.

Abstract: A video/image processing apparatus includes a storage module, a motion estimation module, and a plurality of video/image processing blocks. The storage module is arranged for storing a plurality of images. The motion estimation module is coupled to the storage module, and arranged for retrieving the images from the storage module, and generating motion vectors according to the images. The video/image processing blocks are coupled to the motion estimation module, and arranged for performing a plurality of different video/image processing operations, respectively, wherein each of the video/image processing blocks receives the motion vectors generated from the motion estimation module, and refers to the received motion vectors to perform a designated video/image processing operation.

Abstract: A video processing apparatus includes a storage interface, where information and hardware of a motion estimation module and a motion compensation module are shared between frame rate conversion and video coding operations. The video processing apparatus therefore may perform both the frame rate conversion and video coding operations at the same time or perform them by turns, while requiring fewer resources and a smaller chip area than conventional methods.

Abstract: A method for reducing color noises of a chrominance signal includes the following steps: receiving the chrominance signal; sampling the chrominance signal to generate a plurality of chrominance samples; determining a phase-rotation level between a specific chrominance sample and the chrominance samples; calculating an average value of the chrominance samples; and selectively outputting the average value or the chrominance information of the specific chrominance sample as an output chrominance information to represent the color information of the specific chrominance sample according to the phase-rotation level.

Abstract: An exemplary embodiment of an image processing system is provided, comprising an off-chip memory and an image processor. In the off-chip memory, a plurality of field buffers and frame buffers buffer intermediate data associated with an input image, and the image processor processes the input image and the intermediate data to generate an output image. The image processor processes three stages. In a pre-processing stage, the field buffers are read to perform a pre-process, and the pre-processing results are stored in the field buffers. In a de-interlacing stage, a plurality of first line buffers buffer the pre-processed results read from the field buffers, and a de-interlacing process is performed on the pre-processed results to generate a de-interlaced results. In a post-processing stage, a post-process is performed on the pre-processed results and the de-interlaced results to generate the output image.

Abstract: A memory sharing method provided, comprising determining a type of an input video signal, sharing an SRAM (static random access memory) pool among at least two different processing units of the video system, wherein the SRAM pool comprises a plurality of SRAM units having different sizes, and an SRAM unit size is determined as a common factor of memory sizes required by at least two processing units, and allocating a combination of SRAM units in the SRAM pool to each processing unit processing the input video signal according to the type of the input video signal.

Abstract: A video processing apparatus includes a storage interface, where information and hardware of a motion estimation module and a motion compensation module are shared between frame rate conversion and video coding operations. The video processing apparatus therefore may perform both the frame rate conversion and video coding operations at the same time or perform them by turns, while requiring fewer resources and a smaller chip area than conventional methods.