Abstract: A method for recording a video conference and a video conferencing system are provided. The method includes: providing a user interface to a display device, in which the user interface includes a first area, a second area, and a timeline; in response to obtaining an image corresponding to each of multiple participants from a video signal through a person recognition algorithm, displaying the image of each participant in the first area; in response to converting an audio segment of one of the participants obtained from an audio signal into text content through a voice processing algorithm, associating the text content with the corresponding one of the participants, and based on an order of speaking, displaying the text content in the second area; and adjusting a time length of the timeline according to a recording time of the video conference.

Abstract: Provides a flexible copper clad laminate, which includes a polyimide substrate; a nickel-copper alloy layer; and a copper layer. The nickel-copper alloy layer is formed on at least one side of the polyimide substrate by electroless plating and comprises at least nickel, copper and phosphorus. A content of the copper is more than 30 wt % of the nickel-copper alloy layer, a content of the phosphorus is less than 5 wt % of the nickel-copper alloy layer, and a corrosion potential of the nickel-copper alloy layer in a 0.02 vol % sulfuric acid solution is greater than ?20 mV. The copper layer is formed on a side of the nickel-copper alloy layer away from the polyimide substrate and combined with the nickel-copper alloy layer to form a metal conductive layer. In addition, the aforementioned flexible copper clad laminate has electrochemical corrosion resistance and sufficient peel strength, facilitating the production of flexible printed circuit boards.

Abstract: A method for switching audio reception in a video conference and a video conferencing system are provided. In a case of starting the video conference, relative positions of participants in a conference space and behavioral events of participants are obtained by identifying a video signal. Based on the behavioral event of each participant, whether each participant is in a non-speaking behavior is determined. When a participant is determined to be a non-speaker in the non-speaking behavior, an audio reception range of an audio reception device is adjusted to filter a voice of the non-speaker based on the relative position of the non-speaker in the conference space. When a participant is determined to be a speaker not in the non-speaking behavior, the audio reception range of the audio reception device is adjusted to receive a voice of the speaker based on the relative position of the speaker in the conference space.

Abstract: The embodiments of the disclosure provide a method for reducing computational loading while generating a content and a host. The method includes: obtaining a texture map and a plurality of object texture coordinates, wherein the object texture coordinates correspond to at least one virtual object in the texture map; obtaining a first mesh map corresponding to the texture map; determining a first mesh segment and a second mesh segment within the first mesh map based on the object texture coordinates, wherein the first mesh segment does not correspond to the object texture coordinates, and the second mesh segment corresponds to the object texture coordinates; modifying the first mesh map into a second mesh map via reducing a first segment area of the first mesh segment; and generating a visual content via performing an asynchronous time warp operation on the texture map based on the second mesh map.

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

Abstract: Immunogenic compositions comprising hemagglutinin (HA) variants and/or neuraminidasc (NA) variants, which may be contained in an influenza A virus, and uses thereof for eliciting immune responses against influenza A virus.

Abstract: Disclosed are a headphone and an operating method thereof. The headphone includes a headband frame, a speaker module, a detector and a controller. The speaker module is disposed on the headband frame. The detector is disposed in the headband frame and detect stress changes on the headband frame to output a frequency response voltage value. The controller is electrically connected to the speaker module and the detector, and receives the frequency response voltage value. The controller determines whether the frequency response voltage value is the same as a target frequency response voltage value to read a target frequency response parameter corresponding to the target frequency response voltage value. The controller drives the speaker module according to the target frequency response parameter.

Abstract: An example foldable mobile computing device includes a first side including a first power storage device coupled to a first regulator. The device includes a second side including a second power storage device coupled to a second regulator and connected in parallel with the first power storage device. The second side is configured to articulate relative to the first side about a hinge. The device includes processing circuitry configured to determine a power storage capacity of the first power storage device and to determine a power storage capacity of the second power storage device. The device is also configured to adjust, based on the power storage capacity of the first power storage device and the power storage capacity of the second power storage device, at least one of an impedance of the first regulator or an impedance of the second regulator.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

Abstract: The present disclosure relates to a low glycosylated spike protein and a vaccine designed to express the spike protein in vivo. The present disclosure also teaches a method for generating an immune response by utilizing the low glycosylated spike protein, which provides a broader protection across different variants. A method for identifying a glycan-shielded conserved peptide of a glycoprotein is also disclosed.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes etching a substrate to form a recess within a surface of the substrate. An epitaxial material is formed within the recess, a capping structure is formed on the epitaxial material, and a capping layer is formed onto the capping structure. The capping layer laterally extends past an outermost sidewall of the capping structure. Dopants are implanted into the epitaxial material. Implanting the dopants into the epitaxial material forms a first doped region having a first doping type and a second doped region having a second doping type.

Abstract: Various embodiments of the present application are directed towards an integrated chip structure. The integrated chip structure includes a bottom electrode over a substrate, a top electrode over the bottom electrode, and a capacitor insulator structure between the bottom electrode and the top electrode. The capacitor insulator structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. The first dielectric layer includes a first dielectric material. The second dielectric layer includes a second dielectric material that is different than the first dielectric material. The second dielectric material is an amorphous solid. The third dielectric layer includes the first dielectric material.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A method and a system for refreshing a flash memory device are provided. The system mainly includes a host, and a main control unit and a plurality of flash memory units arranged in the flash memory device. The method includes the following steps: providing a performance value of the plurality of flash memory units from the main control unit to the host; providing a refresh command from the host to the main control unit when the performance value is lower than a pre-determined value; and controling the plurality of flash memory units, by the the main control unit, to stop current operations, and executing a refresh operation on the plurality of flash memory units.

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area.

Abstract: The present invention relates to a cholesteric liquid crystal display device, and a control method. The cholesteric liquid crystal display device includes a cholesteric liquid crystal display module, a solar battery unit, and a control unit. The control unit further includes an ambient energy management module and an energy storage module. The solar battery unit provides electrical energy to the management module. And the ambient energy management module stores electrical energy in the energy storage module. When it is necessary to refresh the images of the cholesteric liquid crystal display module, and the potential difference of the energy storage module reaches the charging cut-off voltage. The energy storage module can discharge the stored electrical energy to provide the electrical energy required by the cholesteric liquid crystal display module to refresh the image.