Abstract: The present invention relates to a cholesteric liquid crystal display device, and a control method. The cholesteric liquid crystal display device includes a cholesteric liquid crystal display module, a solar battery unit, and a control unit. The control unit further includes an ambient energy management module and an energy storage module. The solar battery unit provides electrical energy to the management module. And the ambient energy management module stores electrical energy in the energy storage module. When it is necessary to refresh the images of the cholesteric liquid crystal display module, and the potential difference of the energy storage module reaches the charging cut-off voltage. The energy storage module can discharge the stored electrical energy to provide the electrical energy required by the cholesteric liquid crystal display module to refresh the image.

Abstract: A projection calibration method includes transmitting a calibration command to an edge node by a center node, acquiring a projection image of a test pattern image by the edge node, performing image processing on the acquired projection n image by the edge node based on the calibration command to get a calibration parameter data, transmitting the calibration parameter data to the center node by the edge node, and outputting a calibration result to a projector by the center node based on the calibration parameter data.

Abstract: The disclosed and claimed subject matter relates to a stripping composition having a controlled oxide etch and ITO (Indium Tin oxide) etch as well as sidewall polymer and polymer etch residue removal capability and to a process for stripping and etching utilizing the composition.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

Abstract: A vacuum breaker valve includes a valve body and a vacuum breaking device mounted in the valve body. The valve body has a periphery provided with multiple air vent holes corresponding to the vacuum breaking device. The vacuum breaking device includes a mounting barrel, an elastic member, a braking member, a mounting plate, a water stop gasket, and a water inlet disk. The vacuum breaking device is assembled previously and then directly fitted into the valve body to construct the vacuum breaker valve. Thus, the vacuum breaking device and the valve body are combined together for a whole sale or the vacuum breaking device and the valve body are sold individually.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure disposed on a semiconductor substrate. A photodetector is disposed at least partially in the epitaxial structure. A first capping layer is disposed on the semiconductor substrate and covers the epitaxial structure. A second capping layer is disposed vertically between the first capping layer and the epitaxial structure. The first capping layer extends laterally past outermost sidewalls of the epitaxial structure and the second capping layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a bottom electrode over a substrate. A top electrode overlies the bottom electrode. A capping structure is disposed between the top electrode and the bottom electrode. The capping structure comprises a diffusion barrier layer vertically stacked with a metal layer. A switching structure is disposed between the bottom electrode and the capping structure. The switching structure comprises a dielectric layer on the bottom electrode and a first oxygen affinity layer on the dielectric layer. A first Gibbs free energy of the first oxygen affinity layer is less than a second Gibbs free energy of the dielectric layer. A first difference between the first Gibbs free energy and the second Gibbs free energy is less than ?100 kJ/mol.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: The present disclosure relates to novel compounds, methods, and cell-targeting formulations, e.g., a lipid nanoparticle (LNP) for targeted delivery to a tissue or a cell type. The compound and formulation provided herein are designed to have a targeting moiety configured to provide selective delivery features for the formulation and a lipid tail for being incorporated into the bilayer membrane of the formed lipid nanoparticle.

Abstract: The present disclosure provides novel compounds, methods, and cell targeting mRNA vaccine formulations for targeted delivery, such as delivery to dendritic cells. The compound and formulation provided herein are designed to have a targeting moiety configured to provide selective delivery features specific for dendritic cells and a lipid tail for incorporated into the bilayer membrane of the formed lipid nanoparticle.

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Abstract: A vacuum breaker valve includes a valve body and a vacuum breaking device mounted in the valve body. The valve body has a periphery provided with multiple air vent holes corresponding to the vacuum breaking device. The vacuum breaking device includes a mounting barrel, an elastic member, a braking member, a mounting plate, a water stop gasket, and a water inlet disk. The vacuum breaking device is assembled previously and then directly fitted into the valve body to construct the vacuum breaker valve. Thus, the vacuum breaking device and the valve body are combined together for a whole sale or the vacuum breaking device and the valve body are sold individually.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.

Abstract: An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

Abstract: The disclosed and claimed subject matter relates to wet etchants exhibiting high copper and cobalt etching rates where the etching rate ratio between the two metals can be varied. The wet etchants have a composition comprising a formulation consisting of: at least one alkanolamine having at least two carbon atoms, at least one amino substituent and at least one hydroxyl substituent with the amino and hydroxyl substituents attached to two different carbon atoms; at least one pH adjuster for adjusting the pH of the formulation to between approximately 9 and approximately 12; at least one chelating agent; and water.

Abstract: A substrate grinding tool is configured to remove material from a semiconductor substrate in a grinding operation. In the grinding operation, the substrate grinding tool uses a combination of mechanical grinding and a chemical etchant to remove material from the semiconductor substrate. The chemical etchant may be heated to a high temperature, which may increase the etch rate of the chemical etchant. The use of the combination of mechanical grinding and the chemical etchant may increase the grinding rate of the substrate grinding tool for grinding semiconductor substrates, may reduce surface roughness for semiconductor substrates that are processed by the substrate grinding tool, and/or may reduce surface damage for semiconductor substrates that are processed by the substrate grinding tool, among other examples.