Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

Abstract: An optical film, an optical film set, a backlight module and a display device are provided. The optical film includes a main body, plural first prism structures and plural second prism structures. The main body has a first optical surface and a second optical surface. The first prism structures are disposed on the first optical surface. Each of the first prism structures extends along a first direction. The second prism structures are disposed on the second optical surface. Each of the second prism structures extends along a second direction. The first direction is different from the second direction.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: A composition and method for removing a metal-containing layer or portion of a layer of a pellicle of an EUV mask are provided. The composition includes water; one or more oxidizing agents; and one or more acids. The method includes forming one or more layers over a silicon substrate with at least one of those layers includes a metal containing layer and removing the metal containing layer by contacting the metal containing layer with the composition of the disclosed and claimed subject matter.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: An acoustic wave element includes: a substrate; a bonding structure on the substrate; a support layer on the bonding structure; a first electrode including a lower surface on the support layer; a cavity positioned between the support layer and the first electrode and exposing a lower surface of the first electrode; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer, wherein at least one of the first electrode and the second electrode includes a first layer and a second layer that the first layer has a first acoustic impedance and a first electrical impedance, the second layer has a second acoustic impedance and a second electrical impedance, wherein the first acoustic impedance is higher than the second acoustic impedance, and the second electrical impedance is lower than the first electrical impedance.

Abstract: A pixel of an image sensor includes: a semiconductor material substrate; a photosensitive region formed in the substrate, the photosensitive region generating photo-induced electrical charge in response to illumination with light; a storage node formed in the substrate proximate to the photosensitive region, the storage node selectively receiving and storing photo-induced electrical charge generated by the photosensitive region; and a shield formed over the storage node which inhibits light from reaching the storage node, the shield including an extension which protrudes into the substrate and surrounds an outer periphery of the storage node.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: A recess etching solution for recess etching a metal wiring in a semiconductor substrate manufacturing process; and a recess etching method employing the same. The recess etching solution is for applying recess etching to a surface of a cobalt-containing metal layer embedded in a via or a trench formed in a semiconductor substrate, and contains (A) an organic acid, one of or both of (B) a nitrogen-containing heterocyclic compound and (C) an organic solvent, and (D) water. The recess etching method includes applying recess etching to a surface of a cobalt-containing metal layer by bringing the recess etching solution into contact with the surface of the cobalt-containing metal layer embedded in a via or a trench formed in a semiconductor substrate.

Abstract: A power semiconductor device includes a first electrode, a substrate, a first epitaxy layer, a second epitaxy layer, a gate electrode, and a second electrode. The substrate is located on the first electrode, and the substrate includes an active region and a termination region surrounding the active region. The first epitaxy layer is located on the substrate, and the first epitaxy layer has a first conductive type. The first epitaxy layer includes a first doped area and a second doped area. The first doped area has the first conductive type and is located in the termination region and the active region. The second doped area has a second conductive type and is located in the termination region. The second epitaxy layer is located on the first epitaxy layer. The gate electrode and the second electrode are located on the second epitaxy layer and are in the active region.

Abstract: A power semiconductor device includes a first electrode, a substrate, a first epitaxy layer, a second epitaxy layer, a gate electrode, and a second electrode. The substrate is located on the first electrode, and the substrate includes an active region and a termination region surrounding the active region. The first epitaxy layer is located on the substrate, and the first epitaxy layer has a first conductive type. The first epitaxy layer includes a first doped area and a second doped area. The first doped area has the first conductive type and is located in the termination region and the active region. The second doped area has a second conductive type and is located in the termination region. The second epitaxy layer is located on the first epitaxy layer. The gate electrode and the second electrode are located on the second epitaxy layer and are in the active region.

Abstract: A method of single crystal growth includes disposing a polycrystalline source material in a chamber of a single crystal growth apparatus, disposing a seed layer in the chamber of the single crystal growth apparatus, wherein the seed layer is fixed below a lid of the single crystal growth apparatus, heating the polycrystalline source material by a heater of the single crystal growth apparatus to deposit a semiconductor material layer on the seed layer, and after depositing the semiconductor material layer, providing a coolant gas at a backside of the lid to cool down the seed layer and the semiconductor material layer.

Abstract: A method for making a three-dimensional semiconductor structure includes: providing a substrate, forming a first insulating layer on the substrate, and defining at least one channel hole in the first insulating layer; forming a first epitaxial layer in each channel hole and forming a second epitaxial layer stacked on the first epitaxial layer; forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, forming another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer, and forming another second epitaxial layer stacking on the another first epitaxial layer; repeating to form a plurality of sacrificial layers and a plurality of second insulating layers alternately stacked on the first insulating layer, and repeating to form a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked on the substrate.

Abstract: A flexible circuit board includes liquid crystal polymer (LCP) layers and metal layers including circuit routes. Each of the LCP layers includes via structures. The metal layers and the LCP layers are alternatively stacked to form a multi-layer structure. Adjacent metal layers are electrically connected through the via structures. Some via structures of different LCP layers are substantially aligned with one another to form a stack of via structures. Each of the via structures includes openings filled with conductive material. The size of the opening fulfils the following equation: Vb?cos(Bh/Vh)*Vt/k*2, where Vb is a diameter of a smaller aperture, Vt is a diameter of a bigger aperture, Vh is a combined thickness of a LCP layer and a metal layer, Bh is a thickness of a LCP layer and k is a tensile modulus.

Abstract: An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

Abstract: A method of single crystal growth includes disposing a polycrystalline source material in a chamber of a single crystal growth apparatus, disposing a seed layer in the chamber of the single crystal growth apparatus, wherein the seed layer is fixed below a lid of the single crystal growth apparatus, heating the polycrystalline source material by a heater of the single crystal growth apparatus to deposit a semiconductor material layer on the seed layer, and after depositing the semiconductor material layer, providing a coolant gas at a backside of the lid to cool down the seed layer and the semiconductor material layer.