Abstract: Provides a flexible copper clad laminate, which includes a polyimide substrate; a nickel-copper alloy layer; and a copper layer. The nickel-copper alloy layer is formed on at least one side of the polyimide substrate by electroless plating and comprises at least nickel, copper and phosphorus. A content of the copper is more than 30 wt % of the nickel-copper alloy layer, a content of the phosphorus is less than 5 wt % of the nickel-copper alloy layer, and a corrosion potential of the nickel-copper alloy layer in a 0.02 vol % sulfuric acid solution is greater than ?20 mV. The copper layer is formed on a side of the nickel-copper alloy layer away from the polyimide substrate and combined with the nickel-copper alloy layer to form a metal conductive layer. In addition, the aforementioned flexible copper clad laminate has electrochemical corrosion resistance and sufficient peel strength, facilitating the production of flexible printed circuit boards.

Abstract: A power supply device includes a control board disposed within the chassis. An input connector and an output connector are disposed within the chassis and are electrically connected to the control board. A fan module includes a fan frame and a fan connector disposed on the outer surface of the fan frame. A flexible printed circuit board includes a conducting section, a fan connecting section and a lighting connecting section. The conducting section is electrically connected to the control board, fan connecting section and the lighting connecting section. The fan connecting section is electrically connected to the fan connector. The light-guiding handle is coupled to the chassis and disposed on the lighting connecting section to face the light-guiding handle.

Abstract: An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

Abstract: A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

Abstract: A semiconductor with 3D flash memory storing cells includes a stack structure in each storing cell, a blocking layer, at least one floating gate layer, a tunnel dielectric layer, and a channel layer. The stack structure includes at least one control gate layer, at least one dielectric layer, and at least one erasing layer. The blocking layer is coplanar with the control gate layer. The floating layer is received in the blocking layer, and insulates the control gate layer by the blocking layers. The tunnel dielectric layer covers sides of the blocking layer and the floating gate layer. The channel layer is placed on a side of the tunnel electric layer. When the storing cell executes a data reading and writing process, a voltage is applied on the erasing layer to reduce a series resistance of the channel layer for rapid conduction by the semiconductor.

Abstract: A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

Abstract: A recess etching solution for recess etching a metal wiring in a semiconductor substrate manufacturing process; and a recess etching method employing the same. The recess etching solution is for applying recess etching to a surface of a cobalt-containing metal layer embedded in a via or a trench formed in a semiconductor substrate, and contains (A) an organic acid, one of or both of (B) a nitrogen-containing heterocyclic compound and (C) an organic solvent, and (D) water. The recess etching method includes applying recess etching to a surface of a cobalt-containing metal layer by bringing the recess etching solution into contact with the surface of the cobalt-containing metal layer embedded in a via or a trench formed in a semiconductor substrate.

Abstract: A power semiconductor device includes a first electrode, a substrate, a first epitaxy layer, a second epitaxy layer, a gate electrode, and a second electrode. The substrate is located on the first electrode, and the substrate includes an active region and a termination region surrounding the active region. The first epitaxy layer is located on the substrate, and the first epitaxy layer has a first conductive type. The first epitaxy layer includes a first doped area and a second doped area. The first doped area has the first conductive type and is located in the termination region and the active region. The second doped area has a second conductive type and is located in the termination region. The second epitaxy layer is located on the first epitaxy layer. The gate electrode and the second electrode are located on the second epitaxy layer and are in the active region.

Abstract: A power semiconductor device includes a first electrode, a substrate, a first epitaxy layer, a second epitaxy layer, a gate electrode, and a second electrode. The substrate is located on the first electrode, and the substrate includes an active region and a termination region surrounding the active region. The first epitaxy layer is located on the substrate, and the first epitaxy layer has a first conductive type. The first epitaxy layer includes a first doped area and a second doped area. The first doped area has the first conductive type and is located in the termination region and the active region. The second doped area has a second conductive type and is located in the termination region. The second epitaxy layer is located on the first epitaxy layer. The gate electrode and the second electrode are located on the second epitaxy layer and are in the active region.

Abstract: A method for making a three-dimensional semiconductor structure includes: providing a substrate, forming a first insulating layer on the substrate, and defining at least one channel hole in the first insulating layer; forming a first epitaxial layer in each channel hole and forming a second epitaxial layer stacked on the first epitaxial layer; forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, forming another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer, and forming another second epitaxial layer stacking on the another first epitaxial layer; repeating to form a plurality of sacrificial layers and a plurality of second insulating layers alternately stacked on the first insulating layer, and repeating to form a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked on the substrate.

Abstract: A method of single crystal growth includes disposing a polycrystalline source material in a chamber of a single crystal growth apparatus, disposing a seed layer in the chamber of the single crystal growth apparatus, wherein the seed layer is fixed below a lid of the single crystal growth apparatus, heating the polycrystalline source material by a heater of the single crystal growth apparatus to deposit a semiconductor material layer on the seed layer, and after depositing the semiconductor material layer, providing a coolant gas at a backside of the lid to cool down the seed layer and the semiconductor material layer.

Abstract: A flexible circuit board includes liquid crystal polymer (LCP) layers and metal layers including circuit routes. Each of the LCP layers includes via structures. The metal layers and the LCP layers are alternatively stacked to form a multi-layer structure. Adjacent metal layers are electrically connected through the via structures. Some via structures of different LCP layers are substantially aligned with one another to form a stack of via structures. Each of the via structures includes openings filled with conductive material. The size of the opening fulfils the following equation: Vb?cos(Bh/Vh)*Vt/k*2, where Vb is a diameter of a smaller aperture, Vt is a diameter of a bigger aperture, Vh is a combined thickness of a LCP layer and a metal layer, Bh is a thickness of a LCP layer and k is a tensile modulus.

Abstract: An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

Abstract: A method of single crystal growth includes disposing a polycrystalline source material in a chamber of a single crystal growth apparatus, disposing a seed layer in the chamber of the single crystal growth apparatus, wherein the seed layer is fixed below a lid of the single crystal growth apparatus, heating the polycrystalline source material by a heater of the single crystal growth apparatus to deposit a semiconductor material layer on the seed layer, and after depositing the semiconductor material layer, providing a coolant gas at a backside of the lid to cool down the seed layer and the semiconductor material layer.

Abstract: A semiconductor with 3D flash memory storing cells includes a stack structure in each storing cell, a blocking layer, at least one floating gate layer, a tunnel dielectric layer, and a channel layer. The stack structure includes at least one control gate layer, at least one dielectric layer, and at least one erasing layer. The blocking layer is coplanar with the control gate layer. The floating layer is received in the blocking layer, and insulates the control gate layer by the blocking layers. The tunnel dielectric layer covers sides of the blocking layer and the floating gate layer. The channel layer is placed on a side of the tunnel electric layer. When the storing cell executes a data reading and writing process, a voltage is applied on the erasing layer to reduce a series resistance of the channel layer for rapid conduction by the semiconductor.

Abstract: A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

Abstract: A method for making a three-dimensional semiconductor structure includes: providing a substrate, forming a first insulating layer on the substrate, and defining at least one channel hole in the first insulating layer; forming a first epitaxial layer in each channel hole and forming a second epitaxial layer stacked on the first epitaxial layer; forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, forming another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer, and forming another second epitaxial layer stacking on the another first epitaxial layer; repeating to form a plurality of sacrificial layers and a plurality of second insulating layers alternately stacked on the first insulating layer, and repeating to form a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked on the substrate.

Abstract: An image processing device includes a flicker estimating circuit, a control circuit and an image processing circuit. The flicker estimating circuit estimates a flicker level of a frame according to at least one set of information corresponding to the frame to generate an estimated flicker result. The control circuit is coupled to the flicker estimating circuit, and generates at least one control signal according to the flicker level. The image processing circuit is coupled to the control circuit, and performs image processing on the frame according to the control signal.

Abstract: A portable device for controlling an external electrical adjustable apparatus is provided. The portable device has a case, a signal transmitter connected to the electrical adjustable apparatus, a tilt sensor sensing a tilted angle and a controlling operation, a memory storing a threshold angle and a processor. The processor generates a controlling signal according to the controlling operation, and transmitting the controlling signal to an electrical adjustable apparatus for making the electrical adjustable apparatus raise/lower. The processor further determines that the electrical adjustable apparatus has collision when receiving a controlling signal used to control the electrical adjustable apparatus and the tilted angle is not less than the threshold angle, and sends a stopping signal to the electrical adjustable apparatus via the signal transmitter for making the electrical adjustable apparatus stop raising/lowering when determining that the electrical adjustable apparatus has collision.

Abstract: A connecting device for a chainring of a bicycle is disclosed, including a connecting disc, a shaft, and a crank. The connecting disc is adapted to be engaged with a chainring, and has an axial bore, a bulging portion bulging from a central portion of the connecting disc, and a surrounding portion, which is flat, and surrounds an outer periphery of the bulging portion. The shaft passes through the axial bore to be fixedly engaged with the connecting disc. The shaft has a connecting end. The crank has a connecting end engaged with the connecting end of the shaft, and a bearing end adapted to bear an external force to make the crank rotate around the shaft. Whereby, the amount of materials used to make the connecting device is decreased. At the same time, the manufacturing cost, the size, and the weight of the connecting device are all reduced.