Patents by Inventor Chung-Yi Lin
Chung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240369759Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: ApplicationFiled: July 16, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Patent number: 12125548Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.Type: GrantFiled: July 25, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hao Huang, Katherine H. Chiang, Cheng-Yi Wu, Chung-Te Lin
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Publication number: 20240324714Abstract: An insole with wireless charging system includes a pressure sensing layer arranged on the insole, a sensing device is formed in the insole to detect speed, distance, direction, acceleration, angular orientation or any combination thereof. An inductive coil is formed in the insole for wireless charging a battery.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: Yao-Sheng Chou, Chung-Yuan Wu, Hsiao-Yi Lin
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Publication number: 20240331795Abstract: It is checked, using machine learning, whether at least one fail bit in a memory block of a memory is unrepairable, according to a location of the at least one fail bit, and an available repair resource in the memory. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a CSP containing constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to the checking, using the machine learning, indicating that the at least one fail bit is unrepairable, the memory block is marked as unrepairable or the memory is rejected, without making further determinations as to repairability of the memory block.Type: ApplicationFiled: June 11, 2024Publication date: October 3, 2024Inventors: Katherine H. CHIANG, Chien-Hao HUANG, Cheng-Yi WU, Chung-Te LIN
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Patent number: 12105323Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: GrantFiled: July 25, 2023Date of Patent: October 1, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20240321780Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.Type: ApplicationFiled: June 4, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
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Publication number: 20240321765Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.Type: ApplicationFiled: June 6, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
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Patent number: 12098502Abstract: A thermoplastic artificial leather includes a thermoplastic composite laminate and a textile base. The thermoplastic composite laminate includes a foamed thermoplastic elastic layer, an unfoamed thermoplastic elastic layer and a thermoplastic adhesive layer. The foamed thermoplastic elastic layer has a first surface, a second surface and a plurality of foamed structures. The second surface is opposite to the first surface. The unfoamed thermoplastic elastic layer is disposed on the first surface of the foamed thermoplastic elastic layer. The thermoplastic adhesive layer is disposed on the second surface of the foamed thermoplastic elastic layer. The textile base is laminated on the thermoplastic adhesive layer of the thermoplastic composite laminate.Type: GrantFiled: July 28, 2020Date of Patent: September 24, 2024Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.Inventors: Chung-Chih Feng, Chih-Yi Lin, Kao-Lung Yang, Chi-Chin Chiang
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Patent number: 12083284Abstract: A respiratory system includes a gas supply unit and a heating and humidifying unit. The gas supply unit includes a gas supply port; the heating and humidifying unit is detachably combined with the gas supply unit. The heating and humidifying unit includes a base, an adapter and a water tank. The base includes a control element, and the adapter is combined with the base and can rotate at least 90 degrees relative to the base. The water tank is detachably combined with the base, and the water tank includes a gas inlet and a gas outlet, wherein when the water tank is combined with the base, the gas inlet penetrates through an aperture of the base to be fluidly connected to the gas supply port, and the gas outlet is fluidly connected to the adapter.Type: GrantFiled: September 25, 2020Date of Patent: September 10, 2024Assignee: APEX MEDICAL CORP.Inventors: Chun-Yen Lin, Chung-Yi Lin, Jhih-Teng Yao, Chih-Tsan Chien, Tsung-Chung Kan, Hao-Yu Chan
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Publication number: 20240290734Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan TAI, Ting-Ting KUO, Yu-Chih HUANG, Chih-Wei LIN, Hsiu-Jen LIN, Chih-Hua CHEN, Ming-Da CHENG, Ching-Hua HSIEH, Hao-Yi TSAI, Chung-Shi LIU
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Patent number: 12069851Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.Type: GrantFiled: March 17, 2020Date of Patent: August 20, 2024Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chung-Yen Chou, Chih-Yuan Chen, Qinfu Zhang, Chao-Wei Lin, Chia-Yi Chu, Jen-Chieh Cheng, Jen-Kuo Wu, Huixian Lai
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Patent number: 12051634Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.Type: GrantFiled: July 21, 2023Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
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Patent number: 12040283Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.Type: GrantFiled: April 19, 2023Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
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Publication number: 20240222352Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.Type: ApplicationFiled: January 29, 2024Publication date: July 4, 2024Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
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Publication number: 20240079439Abstract: A pixel of an image sensor includes: a semiconductor material substrate; a photosensitive region formed in the substrate, the photosensitive region generating photo-induced electrical charge in response to illumination with light; a storage node formed in the substrate proximate to the photosensitive region, the storage node selectively receiving and storing photo-induced electrical charge generated by the photosensitive region; and a shield formed over the storage node which inhibits light from reaching the storage node, the shield including an extension which protrudes into the substrate and surrounds an outer periphery of the storage node.Type: ApplicationFiled: January 4, 2023Publication date: March 7, 2024Inventors: Chung-Yi Lin, Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 11923353Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.Type: GrantFiled: July 27, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
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Patent number: 11894263Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: GrantFiled: October 7, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Patent number: 11864369Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.Type: GrantFiled: March 10, 2022Date of Patent: January 2, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Hung-Yu Ye, Chung-Yi Lin, Yun-Ju Pan, Chee-Wee Liu
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Publication number: 20230386899Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Publication number: 20230369152Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.Type: ApplicationFiled: July 21, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai