Patents by Inventor Chung-Yi Lin

Chung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250046637
    Abstract: A device and a method for robotic arm automatic correction are disclosed. A main structure includes a robotic arm including an optical photographing mechanism, and a wafer storage mechanism at one side of the robotic arm and including a graphic data code. The optical photographing mechanism is in information connection with an optical recognition module that includes a data code analysis unit, an object distance analysis unit, and a wafer center analysis unit. A user uses the optical photographing mechanism to photograph the graphic data code for implementing a first round of position correction for the robotic arm. Then, the optical photographing mechanism photographs a wafer and performs an operation of focusing for calculation of a distance between the robotic arm and a center point of the wafer by means of the object distance analysis unit in combination with the wafer center analysis unit for a second round of correction.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Cheng-Hsiang LU, Chung-Hsien LU, Yu-Hsin LIU, Jen-Wei CHANG, Jyun-Yi LU, Bo-Wen LIN
  • Patent number: 12217999
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Cheng-Hsin Chen, Chung Chieh Ting, Che-Yi Lin, Clark Lee
  • Publication number: 20250038103
    Abstract: A structure of an MIM capacitor and a heat sink include a dielectric layer. The dielectric layer includes a capacitor region and a heat dispensing region. A bottom electrode is embedded in the dielectric layer. A first heat conductive layer covers the dielectric layer. A capacitor dielectric layer is disposed on the first heat conductive layer within the capacitor region. A second heat conductive layer covers and contacts the capacitor dielectric layer and the first heat conductive layer. A top electrode is disposed within the capacitor region and the heat dispensing region and covers the second heat conductive layer. A first heat sink is disposed within the heat dispensing region and contacts the top electrode. A second heat sink is disposed within the heat dispensing region and contacts the first heat conductive layer and the second heat conductive layer.
    Type: Application
    Filed: August 14, 2023
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Chung-Yi Chiu
  • Publication number: 20250040158
    Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.
    Type: Application
    Filed: August 15, 2023
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Chung-Yi Chiu
  • Patent number: 12210200
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12211699
    Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yeh-Sheng Lin, Chang-Mao Wang, Chun-Chi Yu, Chung-Yi Chiu
  • Publication number: 20240362392
    Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Shu-Wei Chung, Tung-Heng Hsieh, Chung-Hui Chen, Chung-Yi Lin
  • Patent number: 12083284
    Abstract: A respiratory system includes a gas supply unit and a heating and humidifying unit. The gas supply unit includes a gas supply port; the heating and humidifying unit is detachably combined with the gas supply unit. The heating and humidifying unit includes a base, an adapter and a water tank. The base includes a control element, and the adapter is combined with the base and can rotate at least 90 degrees relative to the base. The water tank is detachably combined with the base, and the water tank includes a gas inlet and a gas outlet, wherein when the water tank is combined with the base, the gas inlet penetrates through an aperture of the base to be fluidly connected to the gas supply port, and the gas outlet is fluidly connected to the adapter.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 10, 2024
    Assignee: APEX MEDICAL CORP.
    Inventors: Chun-Yen Lin, Chung-Yi Lin, Jhih-Teng Yao, Chih-Tsan Chien, Tsung-Chung Kan, Hao-Yu Chan
  • Patent number: 12073165
    Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wei Chung, Tung-Heng Hsieh, Chung-Hui Chen, Chung-Yi Lin
  • Patent number: 12051634
    Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20240222352
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Application
    Filed: January 29, 2024
    Publication date: July 4, 2024
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Publication number: 20240079439
    Abstract: A pixel of an image sensor includes: a semiconductor material substrate; a photosensitive region formed in the substrate, the photosensitive region generating photo-induced electrical charge in response to illumination with light; a storage node formed in the substrate proximate to the photosensitive region, the storage node selectively receiving and storing photo-induced electrical charge generated by the photosensitive region; and a shield formed over the storage node which inhibits light from reaching the storage node, the shield including an extension which protrudes into the substrate and surrounds an outer periphery of the storage node.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 7, 2024
    Inventors: Chung-Yi Lin, Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 11923353
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 11894263
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
  • Patent number: 11864369
    Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 2, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Yu Ye, Chung-Yi Lin, Yun-Ju Pan, Chee-Wee Liu
  • Publication number: 20230386899
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
  • Publication number: 20230369313
    Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Ting-Yun Wu, Yen-Sen Wang, Chung-Yi Lin
  • Publication number: 20230369152
    Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11756849
    Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11735579
    Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Yun Wu, Yen-Sen Wang, Chung-Yi Lin