Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: An inspection apparatus for inspecting a light-emitting diode wafer is provided. The inspection apparatus includes a Z-axis translation stage, a sensing probe, a height measurement module, a carrier, an illumination light source, and a processing device. The sensing probe is integrated with the Z-axis translation stage. The Z-axis translation stage is adapted to drive the sensing probe to move in a Z axis. The sensing probe includes a photoelectric sensor, a beam splitter, and a photoelectric sensing structure. One of the photoelectric sensor of the sensing probe and the height measurement module is adapted to receive a light beam penetrating the beam splitter, and the other one of the photoelectric sensor of the sensing probe and the height measurement module is adapted to receive a light beam reflected by the beam splitter. The carrier is configured to carry the light-emitting diode wafer. The illumination light source is configured to emit an illumination beam to irradiate the light-emitting diode wafer.

Abstract: A semiconductor structure includes a substrate; a seal ring region around a circuit region over the substrate, wherein the seal ring region includes a sealing region and a transition region, and wherein the transition region is disposed between the sealing region and the circuit region; and a stack of metal layers disposed over the circuit region, the transition region and the sealing region. A metal layer of the stack of metal layers includes metal seal rings disposed in the sealing region including a first section along a first direction and a second section along a second direction, wherein the second direction is substantially perpendicular to the first direction; and metal transition lines disposed in the transition region along the first section and the second section, wherein the metal transition lines are oriented lengthwise along the first direction.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.

Abstract: A method of preparing a layout for manufacturing a semiconductor device includes receiving a layout that includes a plurality of metal interconnects, identifying a first set of metal interconnects from the metal interconnects corresponding to a first patterning process and a second set of metal interconnects from the metal interconnects corresponding to a second patterning process, identifying a first set of floating metal portions in the first set of metal interconnects and a second set of floating metal portions in the second set of metal interconnects, and removing the second set of floating metal portions from the layout, while the first set of floating metal portions remains in the layout.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

Abstract: Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.

Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.

Abstract: Provided are a three-dimensional (3D) memory device and a manufacturing method thereof. The 3D memory device includes a gate stacked structure, a channel layer, a charge storage structure, an electrode layer and a capacitor dielectric layer. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The gate stacked structure has at least one channel hole and at least one capacitor trench. The channel layer is disposed on the sidewall of the at least one channel hole. The charge storage structure is disposed between the channel layer and the sidewall of the at least one channel hole. The electrode layer is disposed on the sidewall of the at least one capacitor trench. The capacitor dielectric layer is disposed between the electrode layer and the sidewall of the at least one capacitor trench.

Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.

Abstract: A device includes a first semiconductor fin, a second semiconductor fin, first source/drain features, second source/drain features, a first gate structure, a second gate structure, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first semiconductor fin and the second semiconductor fin are adjacent to each other. The first source/drain features are on opposite sides of the first semiconductor fin. The second source/drain features are on opposite sides of the second semiconductor fin. The first gate structure is over the first semiconductor fin. The second gate structure is over the second semiconductor fin. The first VGAA transistor is over one of the first source/drain features. The second VGAA transistor is over one of the second source/drain features.

Abstract: A device includes a first semiconductor fin, a second semiconductor fin, first source/drain features, second source/drain features, a first gate structure, a second gate structure, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first semiconductor fin and the second semiconductor fin are adjacent to each other. The first source/drain features are on opposite sides of the first semiconductor fin. The second source/drain features are on opposite sides of the second semiconductor fin. The first gate structure is over the first semiconductor fin. The second gate structure is over the second semiconductor fin. The first VGAA transistor is over one of the first source/drain features. The second VGAA transistor is over one of the second source/drain features.

Abstract: A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.

Abstract: A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.

Abstract: A respiratory system includes a gas supply unit and a heating and humidifying unit. The gas supply unit includes a gas supply port; the heating and humidifying unit is detachably combined with the gas supply unit. The heating and humidifying unit includes a base, an adapter and a water tank. The base includes a control element, and the adapter is combined with the base and can rotate at least 90 degrees relative to the base. The water tank is detachably combined with the base, and the water tank includes a gas inlet and a gas outlet, wherein when the water tank is combined with the base, the gas inlet penetrates through an aperture of the base to be fluidly connected to the gas supply port, and the gas outlet is fluidly connected to the adapter.

Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.

Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.