Patents by Inventor Chung-Yi Lin

Chung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7361986
    Abstract: A semiconductor package assembly is presented. The assembly comprises a first chip and a second chip. The back surfaces of the first and the second chips are thermally attached through a die attach material. The front surface of the first chip is attached to a substrate through bumps. A heat spreader extends from a surface of the semiconductor package assembly into the semiconductor package assembly and thermally attaches to the back surface of the first chip or the front surface of the second chip. Depending on the sizes of the chips and the location of the bonding pads, the heat spreader may be attached to the back surface of the first chip or the front surface of the second chip.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: April 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsorng-Dih Yuan, Hsin-Yu Pan, Chung-Yi Lin
  • Publication number: 20080013786
    Abstract: A method of tracking a vocal target is disclosed. An image-capturing device is employed to capture an image including the participating targets. Next, an image tracking method is used to determine the image regions where the participating targets are respectively located. The found image regions are compared with the vocal regions of each vocal targets detected by a sound-detecting device. Thus, the positions where the vocal targets are located are precisely detected. Thus, cost of the video system can be effectively reduced and the video image resolution can be effectively promoted.
    Type: Application
    Filed: March 25, 2007
    Publication date: January 17, 2008
    Applicant: COMPAL ELECTRONICS, INC.
    Inventor: Chung-Yi Lin
  • Publication number: 20070090547
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Application
    Filed: January 3, 2006
    Publication date: April 26, 2007
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Publication number: 20070040269
    Abstract: A thermally-enhanced cavity down ball grid array (CDBGA) package is provided. In one embodiment, the CDBGA package comprises a heat dissipating substrate having a heat spreader and a chip carrier, the chip carrier having a cavity therethrough to allow a chip to be attached to the heat spreader. A chip having an active surface and a corresponding back surface, has the back surface of the chip mounted on the heat spreader. A dummy chip is attached to the active surface of the chip. The dummy chip has a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion of the chip. An encapsulant encapsulates the chip and portions of the dummy chip. Dummy chip 90 has a coefficient of thermal expansion (CTE) approximately equal to the coefficient of thermal expansion of the chip 40.
    Type: Application
    Filed: August 22, 2005
    Publication date: February 22, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Frank Wu, Chung-Yi Lin
  • Publication number: 20060270112
    Abstract: A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a recess. A supporting adhesive layer containing a filler is disposed upon the substrate about the lateral periphery of the lower die and substantially filling the recess. In one preferred embodiment, the filler comprises microspheres. In another preferred embodiment, the filler comprises a dummy die, an active die, or a passive die.
    Type: Application
    Filed: July 28, 2006
    Publication date: November 30, 2006
    Inventors: Te-Tsung Chao, Mirng-Ji Lii, Chung-Yi Lin, Abel Chang
  • Patent number: 7138300
    Abstract: An integrated circuit package comprises a semiconductor die located on a substrate in a flip-chip configuration, an encapsulant layer overlying the non-active surface of the semiconductor die and at least a portion of the surface of the substrate adjacent the die, and a heat spreader comprising a thermally conductive material. The heat spreader directly interfaces to a top surface of the encapsulant layer overlying the die and the substrate. This package provides physical protection during handling and reduced die stress and warpage.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: November 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsorng-Dih Yuan, Hsin-Yu Pan, Chung-Yi Lin
  • Patent number: 7116002
    Abstract: A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a recess. A supporting adhesive layer containing a filler is disposed upon the substrate about the lateral periphery of the lower die and substantially filling the recess. In one preferred embodiment, the filler comprises microspheres. In another preferred embodiment, the filler comprises a dummy die, an active die, or a passive die.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 3, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Tsung Chao, Mirng-Ji Lii, Chung-Yi Lin, Abel Chang
  • Publication number: 20060118947
    Abstract: A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises an inorganic substrate, a die disposed on the substrate, the die having a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion of the substrate, a heat spreader disposed over the die, the heat spreader having a coefficient of thermal expansion approximately equal to the coefficients of thermal expansion of the die and the substrate, and at least one stiffener disposed between the substrate and the heat spreader, the stiffener having a coefficient of thermal expansion approximately equal to the coefficients of thermal expansion of the die, substrate, and the heat spreader, whereby warpages in the flip chip ball grid array package are reduced.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Tsorng-Dih Yuan, Chung-Yi Lin, Hsin-Yu Pan
  • Publication number: 20060113663
    Abstract: A semiconductor package assembly is presented. The assembly comprises a first chip and a second chip. The back surfaces of the first and the second chips are thermally attached through a die attach material. The front surface of the first chip is attached to a substrate through bumps. A heat spreader extends from a surface of the semiconductor package assembly into the semiconductor package assembly and thermally attaches to the back surface of the first chip or the front surface of the second chip. Depending on the sizes of the chips and the location of the bonding pads, the heat spreader may be attached to the back surface of the first chip or the front surface of the second chip.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Inventors: Tsorng-Dih Yuan, Hsin-Yu Pan, Chung-Yi Lin
  • Publication number: 20060063300
    Abstract: An integrated circuit package comprises a semiconductor die located on a substrate in a flip-chip configuration, an encapsulant layer overlying the non-active surface of the semiconductor die and at least a portion of the surface of the substrate adjacent the die, and a heat spreader comprising a thermally conductive material. The heat spreader directly interfaces to a top surface of the encapsulant layer overlying the die and the substrate. This package provides physical protection during handling and reduced die stress and warpage.
    Type: Application
    Filed: September 22, 2004
    Publication date: March 23, 2006
    Inventors: Tsorng-Dih Yuan, Hsin-Yu Pan, Chung-Yi Lin
  • Publication number: 20050248019
    Abstract: A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a recess. A supporting adhesive layer containing a filler is disposed upon the substrate about the lateral periphery of the lower die and substantially filling the recess. In one preferred embodiment, the filler comprises microspheres. In another preferred embodiment, the filler comprises a dummy die, an active die, or a passive die.
    Type: Application
    Filed: June 30, 2004
    Publication date: November 10, 2005
    Inventors: Te-Tsung Chao, Mirng-Ji Lii, Chung-Yi Lin, Abel Chang
  • Patent number: 6493902
    Abstract: An automatic wall cleansing apparatus is provided that includes a work platform, a lift unit, a supporting frame, a rotatable brush assembly, a blower unit, and a control unit. The work platform is moved up to a working position, by presetting the control unit. The work platform is lifted to the topmost portion of the building and downwardly executes the cleansing work with the aid of air supplied by the blower unit and a rubbing operation by the rotatable brush assembly. From the supply of detergent, cleansing, spraying of clean water, to drying by hot air, all of the steps are carried out automatically and successively without the need of manual operation.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: December 17, 2002
    Inventor: Chung-Yi Lin
  • Publication number: 20020112312
    Abstract: An automatic wall cleansing apparatus disclosed herein comprises a working platform, a lift unit, a supporting frame, a rotatable brush assembly, a blower unit, and a control unit. The working platform is moved up to a working position. By presetting with the control unit, the working platform is lifted to the topmost portion of the building and downwardly executing cleansing work with the aid of the wind supplied by the blower unit and rubbing operation by rotatable brush assembly. From supply of detergent, cleansing, spraying of clean water to drying by hot wind, all the steps are carried out automatically and successively without need of manual operation.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 22, 2002
    Inventor: Chung-Yi Lin