Patents by Inventor Chung-Yi Lin

Chung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160010374
    Abstract: A pivot mechanism of the synchronous hinge device is applied to a foldable electronic apparatus. The pivot mechanism can be stably rotated and the distance between two shafts of the dual-shaft hinge is shortened, whereby the electronic device can be smoothly rotated and have a miniaturized and lightweight structure. The pivot mechanism includes a driver disposed on a first shaft and a reactor disposed on a second shaft and a link unit. Spur gears and conical (bevel) gears are respectively disposed at two ends of the link unit and the driver and the reactor. The Spur gears and conical (bevel) gears are engaged with each other to transmit power, whereby the first shaft with the driver and the second shaft with the reactor can be stably synchronously rotated in reverse directions.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 14, 2016
    Inventors: AN SZU HSU, WANG JUI LEE, CHUNG YI LIN, YA CHING LIN
  • Publication number: 20160011632
    Abstract: A dual-shaft synchronous transmission device is applied to an electronic apparatus. The distance between the two shafts of the dual-shaft synchronous transmission device is shortened so that the electronic device can be thinned and lightweight. The dual-shaft synchronous transmission device includes a driver and a reactor respectively disposed on a first shaft and a second shaft and a link unit. Spur gear structures or crown gear structures are respectively disposed on the driver and the reactor. Crown gear structures or spur gear structures are respectively disposed at two ends of the link unit correspondingly engaged with the spur gear structures or crown gear structures of the driver and the reactor. When the first shaft and the driver are rotated, the driver rotates the link unit to drive the reactor and the second shaft to synchronously rotate in a direction reverse to the rotational direction of the driver.
    Type: Application
    Filed: August 19, 2014
    Publication date: January 14, 2016
    Inventors: AN SZU HSU, WANG JUI LEE, CHUNG YI LIN, YA CHING LIN
  • Patent number: 9136211
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Chien-Hsun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
  • Patent number: 9118255
    Abstract: A flyback power converter is disclosed. The flyback power converter includes a voltage transformer, a main switch, a synchronous rectification switch, a synchronous rectification control circuit, a sampling circuit and an operation circuit. A control end of the main switch receives a main switch signal so as to control the main switch. The synchronous rectification control circuit transmits control signal to control end of the synchronous rectification switch according to sensing signal received. The sampling circuit samples the state of the synchronous rectification switch so as to generate first logic signal and second logic signal. The operation circuit executes timing for charging/discharging according to the first and the second logic-signal, so as to output switch cut-off pulse signal to a voltage-dividing circuit. If voltage of the sensing signal is lower than predetermined threshold voltage, the synchronous rectification switch enters into cut-off state according to the control signal.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: August 25, 2015
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chung-Yi Lin, Wei-Lieh Lai, Chu-Yi Chou, Yu-Kang Lo, Huang-Jen Chiu, Jing-Yuan Lin
  • Patent number: 9099530
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Compnay, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Publication number: 20150034778
    Abstract: A holder stand includes an adjustable support arm assembly, a holder member pivotally connected to one end of the support arm assembly by a ball-and-socket joint for holding a mobile electronic device, a base member defining a position-limited groove and two retaining holes at two opposite sides of the position-limited groove, and a mating connection block assembly including a housing pivotally connected to an opposite end of the support arm assembly and detachably insertable into the position-limited groove of the base member, two spring members mounted in the housing and two press members coupled to two opposite lateral sides of the housing and respectively forced by the spring members into engagement with the retaining holes of the base member to releasably lock the mating connection block assembly to the base member.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: CHEN-SOURCE INC.
    Inventors: Chung-Yi LIN, Chun-Wei LIN
  • Publication number: 20140346644
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Patent number: 8829653
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Publication number: 20140242794
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Patent number: 8728332
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Publication number: 20140133192
    Abstract: A flyback power converter is disclosed. The flyback power converter includes a voltage transformer, a main switch, a synchronous rectification switch, a synchronous rectification control circuit, a sampling circuit and an operation circuit. A control end of the main switch receives a main switch signal so as to control the main switch. The synchronous rectification control circuit transmits control signal to control end of the synchronous rectification switch according to sensing signal received. The sampling circuit samples the state of the synchronous rectification switch so as to generate first logic signal and second logic signal. The operation circuit executes timing for charging/discharging according to the first and the second logic-signal, so as to output switch cut-off pulse signal to a voltage-dividing circuit. If voltage of the sensing signal is lower than predetermined threshold voltage, the synchronous rectification switch enters into cut-off state according to the control signal.
    Type: Application
    Filed: February 26, 2013
    Publication date: May 15, 2014
    Applicant: LITE-ON TECHNOLOGY CORPORATION
    Inventors: CHUNG-YI LIN, WEI-LIEH LAI, CHU-YI CHOU, YU-KANG LO, HUANG-JEN CHIU, JING-YUAN LIN
  • Publication number: 20140087492
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Application
    Filed: December 4, 2013
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Patent number: 8624346
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Publication number: 20130299984
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 14, 2013
    Inventors: Chung Yu Wang, Chien-Hsun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
  • Publication number: 20130295769
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Patent number: 8492263
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
  • Publication number: 20110185009
    Abstract: The present invention is related to a resource sharing device in a communication system including multiple computing devices. The resource sharing device includes a first interface to couple with a first computing device, a second interface to couple with a second computing device, a function device to provide a function accessible to the first and second computing devices, and a switch device coupled with the function device, the switch device to generate a device descriptor of the function device so that when the first and second computing devices are coupled with the resource sharing device the device descriptor of the function device is sent to the first and second computing devices so as to share the function of the function device to the first and second computing devices and allow the first and second computing devices to be controllable at a time by the function of the function device.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 28, 2011
    Applicant: OURS TECHNOLOGY INC.
    Inventors: Ming-Te Chang, Chung-Yi Lin
  • Publication number: 20110005034
    Abstract: A hinge includes a first connecting member, a shaft fixed to the first connecting member, a second connecting member, and a fastener fixed to the shaft. The shaft includes a shaft body including a first resisting surface and a second resisting surface. The second connecting member defines a through hole for the shaft body rotatably passing through the second connecting member. A first block and a second block extend towards each other from a wall bounding the through hole. The first block faces the second resisting surface, and the second block faces the first resisting surface. When the second connecting member is rotated to a predetermined degree relative to the first connecting member, the first block resists against the second resisting surface, and the second block resists against the second resisting surface.
    Type: Application
    Filed: August 14, 2009
    Publication date: January 13, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHUNG-YI LIN
  • Publication number: 20100269296
    Abstract: A hinge includes a rack, a shaft, a bracket, a first stop member, and a second stop member. The shaft includes a post, and an engaging portion secured to the rack. The bracket defines a pivot hole extending through a first side to a second side of the bracket. The bracket includes a first restricting block extending from the first side and a second restricting block extending towards the second side. The first stop member contacts with the first side of the bracket and forms a first stop portion to resist against the first restricting block of the bracket. The second stop member contacts with the second side of the bracket and forms a second stop portion to resist against the second restricting block of the bracket.
    Type: Application
    Filed: July 2, 2009
    Publication date: October 28, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHUNG-YI LIN
  • Patent number: 7792326
    Abstract: A method of tracking a vocal target is disclosed. An image-capturing device is employed to capture an image including the participating targets. Next, an image tracking method is used to determine the image regions where the participating targets are respectively located. The found image regions are compared with the vocal regions of each vocal targets detected by a sound-detecting device. Thus, the positions where the vocal targets are located are precisely detected. Thus, cost of the video system can be effectively reduced and the video image resolution can be effectively promoted.
    Type: Grant
    Filed: March 25, 2007
    Date of Patent: September 7, 2010
    Assignee: Compal Electronics, Inc.
    Inventor: Chung-Yi Lin