Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: An electrostatic discharge (ESD) protection circuit is provided, which includes multiple ESD clamping circuits and a shunt circuit. The multiple clamping circuits comprise multiple transistors, respectively. The multiple transistors are coupled in series between a first power line and a second power line. A shunt circuit is coupled with a first terminal and a control terminal of a first transistor of the multiple transistors. The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor. The shunt circuit insulates the first terminal of the first transistor from the control terminal of the first transistor during a period outside the period of the ESD event.

Abstract: The present invention discloses an electrical discharge circuit having stable discharging mechanism is provided. A voltage division circuit generates a detection signal based on a voltage input terminal such that a first inverter outputs an inverted detection signal. First PMOS and NMOS circuits are coupled in series between a voltage input terminal and a ground terminal through a first terminal. Second PMOS and NMOS circuits are coupled in series between the voltage input terminal and the ground terminal through a second terminal. A first and a second PMOS control terminals are coupled to the second terminal and the first terminal respectively. A first and a second NMOS control terminals receive the inverted detection signal and the detection signal respectively. A second inverter receives an inverted boost detection signal from the second terminal and outputs a boost detection signal. AN ESD transistor is turned off due to the boost detection signal to discharge the voltage input terminal.

Abstract: An example operation includes one or more of capturing message content from messages between a sender and receiver which comprise information about a transfer of value from the sender to the receiver, detecting information about a compliance check within the message content which indicates whether the transfer of value complies with jurisdictional regulations, and recording the message content including the detected information about the compliance check via a blockchain.

Abstract: The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal.

Abstract: An electrostatic discharge (ESD) protection circuit is provided, which includes multiple ESD clamping circuits and a shunt circuit. The multiple clamping circuits comprise multiple transistors, respectively. The multiple transistors are coupled in series between a first power line and a second power line. A shunt circuit is coupled with a first terminal and a control terminal of a first transistor of the multiple transistors. The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor. The shunt circuit insulates the first terminal of the first transistor from the control terminal of the first transistor during a period outside the period of the ESD event.

Abstract: An electrostatic discharge protection circuit includes a voltage drop circuit, a detector circuit, and a clamping circuit. The voltage drop circuit is configured to generate a second voltage according to a first voltage. The second voltage is smaller than the first voltage. The detector circuit is coupled to the voltage drop circuit. The detector circuit is configured to generate a control signal according to the second voltage and an input voltage. The clamping circuit is coupled to the voltage drop circuit and the detector circuit. The clamping circuit is configured to provide an electrostatic discharge path according to a voltage level of the control signal.

Abstract: A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.

Abstract: An over current protection system includes a first resistor, a second resistor, a third resistor, and an electrostatic discharge circuit. The first resistor includes a first terminal for receiving an input voltage, and a second terminal. The second resistor includes a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a ground terminal. The third resistor includes a first terminal, and a second terminal coupled to the first terminal of the second resistor. The electrostatic discharge circuit is coupled to the first terminal of the third resistor. When the input voltage is an abnormal voltage, the electrostatic discharge circuit is enabled for maintaining a voltage at the second terminal of the third resistor within a normal voltage range.

Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.

Abstract: An example operation includes one or more of capturing message content from messages between a sender and receiver which comprise information about a transfer of value from the sender to the receiver, detecting information about a compliance check within the message content which indicates whether the transfer of value complies with jurisdictional regulations, and recording the message content including the detected information about the compliance check via a blockchain.

Abstract: The present invention relates to a display device comprising: a display panel having a plurality of pixels and a plurality of source lines, wherein each of the pixels is electrically connected to a respective source line; and an SD IC for providing pixel voltages and receiving a noise storage control signal and a noise output control signal; characterized in that the SD IC further comprises a noise reduce module to store voltage levels of the pixel voltages as compensating voltages based on the noise storage control signal and to output the compensating voltages based on the noise output control signal, wherein during a normal period, the SD IC outputs the pixel voltages to the pixels; during a compensation period, the SD IC outputs the compensating voltages to the pixels; wherein the noise output control signal is phased-delayed with respect to the noise storage control signal.

Abstract: A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.

Abstract: An electrostatic discharge protection circuit includes a voltage drop circuit, a detector circuit, and a clamping circuit. The voltage drop circuit is configured to generate a second voltage according to a first voltage. The second voltage is smaller than the first voltage. The detector circuit is coupled to the voltage drop circuit. The detector circuit is configured to generate a control signal according to the second voltage and an input voltage. The clamping circuit is coupled to the voltage drop circuit and the detector circuit. The clamping circuit is configured to provide an electrostatic discharge path according to a voltage level of the control signal.

Abstract: An over current protection system includes a first resistor, a second resistor, a third resistor, and an electrostatic discharge circuit. The first resistor includes a first terminal for receiving an input voltage, and a second terminal. The second resistor includes a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a ground terminal. The third resistor includes a first terminal, and a second terminal coupled to the first terminal of the second resistor. The electrostatic discharge circuit is coupled to the first terminal of the third resistor. When the input voltage is an abnormal voltage, the electrostatic discharge circuit is enabled for maintaining a voltage at the second terminal of the third resistor within a normal voltage range.

Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

Abstract: The present invention relates to a display device comprising: a display panel having a plurality of pixels and a plurality of source lines, wherein each of the pixels is electrically connected to a respective source line; and an SD IC for providing pixel voltages and receiving a noise storage control signal and a noise output control signal; characterized in that the SD IC further comprises a noise reduce module to store voltage levels of the pixel voltages as compensating voltages based on the noise storage control signal and to output the compensating voltages based on the noise output control signal, wherein during a normal period, the SD IC outputs the pixel voltages to the pixels; during a compensation period, the SD IC outputs the compensating voltages to the pixels; wherein the noise output control signal is phased-delayed with respect to the noise storage control signal.