Abstract: A screen calibration method includes acquiring a full screen image displayed on a screen by a camera, acquiring first optical data of a first region of the screen by a sensor, adjusting the first optical data of the first region of the screen according to first calibration parameters for calibrating colors of the first region to approach target optical data, generating second optical data of a second region of the screen according to the full screen image and the first optical data of the first region, generating second calibration parameters according to the target optical data and the second optical data, and adjusting the second optical data of the second region of the screen according to the second calibration parameters for calibrating colors of the second region to approach the target optical data.

Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.

Abstract: A method for adjusting the aspect ratio of a displayed image includes setting a first displayed image range, selectively adjusting the size of the first displayed image range to generate a second displayed image range, driving a plurality of pixels inside the second displayed image range of a display panel to display an image, and disabling a plurality of pixels outside the second displayed image range of the display panel.

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.

Abstract: A screen calibration method includes acquiring a full screen image displayed on a screen by a camera, acquiring first optical data of a first region of the screen by a sensor, adjusting the first optical data of the first region of the screen according to first calibration parameters for calibrating colors of the first region to approach target optical data, generating second optical data of a second region of the screen according to the full screen image and the first optical data of the first region, generating second calibration parameters according to the target optical data and the second optical data, and adjusting the second optical data of the second region of the screen according to the second calibration parameters for calibrating colors of the second region to approach the target optical data.

Abstract: A method for displaying an image includes acquiring a data clock signal, acquiring a vertical synchronization signal, generating a backlight driving signal according to the vertical synchronization signal, and displaying the image by using a display system according to the data clock signal, the vertical synchronization signal, and the backlight driving signal. The data clock signal includes a first square wave. The vertical synchronization signal includes a second square wave. No common time interval is between a first time interval corresponding to the first square wave and a second time interval corresponding to the second square wave. The backlight driving signal includes a composite wave synthesized by a third square wave and at least one pulse width modulation signal.

Abstract: A method for adjusting the aspect ratio of a displayed image includes setting a first displayed image range, selectively adjusting the size of the first displayed image range to generate a second displayed image range, driving a plurality of pixels inside the second displayed image range of a display panel to display an image, and disabling a plurality of pixels outside the second displayed image range of the display panel.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.

Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.

Abstract: A method for displaying an image includes acquiring a data clock signal, acquiring a vertical synchronization signal, generating a backlight driving signal according to the vertical synchronization signal, and displaying the image by using a display system according to the data clock signal, the vertical synchronization signal, and the backlight driving signal. The data clock signal includes a first square wave. The vertical synchronization signal includes a second square wave. No common time interval is between a first time interval corresponding to the first square wave and a second time interval corresponding to the second square wave. The backlight driving signal includes a composite wave synthesized by a third square wave and at least one pulse width modulation signal.

Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.

Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate and spaced apart from the first well, a gate formed on the substrate and positioned in between the first well and the second well, a drain region formed in the first well, a source region formed in the second well, a first doped region formed in the first well and adjacent to the drain region, and a second doped region formed in the first well and spaced apart from both the first doped region and the gate. The first well, the drain region, and the source region include a first conductivity type, the second well, the first doped region and the second doped region include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.

Abstract: An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.