Chunping Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A touch display substrate including: a base substrate having a plurality of pixel regions arranged in the form of an array; a common electrode layer on the base substrate, divided into a plurality of self-capacitive electrodes independent from each other, an orthogonal projection of each of the self-capacitive electrodes on the base substrate covering more than one of the pixel regions; a plurality of touch data lines, arranged in a different layer from the self-capacitive electrodes and each connected with a corresponding one of the self-capacitive electrodes, orthogonal projections of the touch data lines on the base substrate being located within gaps between the plurality of pixel regions; a touch detection chip, connected with each of the self-capacitive electrodes through a corresponding one of the touch data lines, and configured to load a common electrode signal to each of the self-capacitive electrodes in a display period through the corresponding touch data line, and to determine a touch position in
Abstract: An electrostatic protection circuit and a manufacturing method thereof, an array substrate and a display apparatus in the field of display technology are provided. This electrostatic protection circuit includes: a discharge sub-circuit, a buffer sub-circuit and an electrostatic protection line, wherein the electrostatic protection line is a common electrode line; the buffer sub-circuit includes a third transistor and a fourth transistor; a gate and a second electrode of the third transistor are both connected to a first electrode of the fourth transistor, and the first electrode of the third transistor is connected to a signal line; a gate and a second electrode of the fourth transistor are both connected to the signal line.
Abstract: An ESD protection circuit including a TFT arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.
Abstract: The present disclosure provides a package structure of a display component and a display device. The package structure of a display component includes: a base substrate, a display component arranged on a surface of the base substrate, and an package layer covering the display component, in which the package layer includes a second inorganic layer, an organic layer, and a first inorganic layer capable of reducing amount of charges to be trapped sequentially stacked along a direction toward the display component.
Abstract: Embodiments of the present disclosure provide a preparation delivery assembly including: a first substrate, a second substrate, and at least two needles of different lengths, each of which is a hollow needle having a hollow structure; wherein two side walls are provided between the first substrate and the second substrate to define a first chamber for containing a preparation by the first substrate, the second substrate, and the two side walls; at least one first channel that is in communication with the first chamber is provided in the second substrate in a direction substantially perpendicular to the second substrate; and the needles are arranged on a surface of the second substrate distal to the first substrate, and each of the needles is in communication with the first chamber through the at least one first channel to deliver the preparation.
March 26, 2020
February 25, 2021
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
Yongchun LU, Hui LI, Pan LI, Chunping LONG
Abstract: An array substrate, an embedded touch screen, and a display device. The array substrate comprises a base substrate, a touch electrode line located above the base substrate, a touch electrode located above the touch electrode line, and a first insulating layer located between the touch electrode line and the touch electrode. The touch electrode line has a groove portion, the first insulating layer has a via hole, and a connecting portion of the touch electrode extends into the groove portion through the via hole, so as to be electrically connected to the touch electrode line.
Abstract: The present disclosure discloses an electrostatic protection circuit, an array substrate and a display device. In an actual application, a first electrostatic discharge end and a second electrostatic discharge end in the electrostatic protection circuit are respectively coupled with electrostatic protection lines such as a common electrode line, a high-potential reference voltage line and a low potential reference voltage line; a signal line connecting end is coupled with signal lines such as a gate line and a data line; and when the voltage generated by the electrostatic charges accumulated on the signal lines is too large or too small the signal lines and the electrostatic protection lines can be conducted through transistors in the first electrostatic discharge circuit or in the second electrostatic discharge circuit, so that effective electrostatic discharge of the signal lines in a product can be realized without influencing the realization of normal functions of the product.
Abstract: The present disclosure relates to technical field of display. There is disclosed an array substrate, a display panel and a display device. The array substrate includes a plurality of pixels arranged in an array. Two data lines are provided between every two columns of pixels adjacent to each other and a data line is provided at either side of each column of pixels. One gate line is provided between every two rows of pixels adjacent to each other. Each pixel includes two display domains arranged in a column direction and each display domain is correspondingly connected with a switch device.
Abstract: Some embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate includes a test circuit located in a non-display area, wherein the test circuit includes at least one stage of subcircuit, and the subcircuit includes at least one demux; except the first stage of subcircuit, the input ends of the demuxes in the subcircuit are connected with corresponding output ends of the demuxes in the previous stage of subcircuit; except the last stage of subcircuit, the output ends of the demuxes in the subcircuit are connected with corresponding input ends of the demuxes in the next stage of subcircuit; and the input end of the demux in the first stage of subcircuit is connected with a test terminal, and the output ends of the demuxes in the last stage of subcircuit are connected with signal lines in a display area.
Abstract: A pixel structure includes a plurality of pixels, and each of the plurality of pixels includes at least one green sub-pixel and at least one other color sub-pixel. A display region determined by the plurality of pixels includes a main display region and at least one special-shaped display region. A boundary of the at least one special-shaped display region includes an arc-shaped edge. The plurality of pixels include a plurality of pixels disposed in the main display region and a plurality of pixels disposed in the at least one special-shaped display region. In each pixel disposed at a corresponding position of the arc-shaped edge, the at least one green sub-pixel is disposed at a side of the at least one other color sub-pixel proximate to the arc-shaped edge.
Abstract: The present disclosure relates to an array substrate comprising a substrate body provided, on a perimeter edge thereof, with a sealant coating region to be coated with a sealant, and the sealant coating region comprises a first region provided with a metal trace structure, and further comprises a region provided with a metal structure, a difference between an area of the metal structure and that of the metal trace structure being smaller than a threshold.
Abstract: The present disclosure provides a thin film transistor, a display panel and a method for manufacturing the thin film transistor. The thin film transistor includes an active layer and a source-drain electrode layer, the source-drain electrode layer includes a first electrode having at least one first electrode strip and a second electrode having at least one second electrode strip, the at least one first electrode strip and the at least one second electrode strip are alternately arranged at intervals, and at least an insulating part of a layer where the active layer is located is provided with an insulating material, and the insulating part is located at an orthographic projection of at least a part of a region between a free end of the first electrode strip, which is proximal to the second electrode, and the second electrode, on the layer where the active layer is located.
Abstract: The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.
Abstract: An array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area surrounding the display area. The array substrate further includes a plurality of signal lines located in the display area, a plurality of test signal lines and a plurality of test control transistors located in the non-display area and respectively corresponding to the plurality of signal lines. Each of the signal lines is connected to a respective one of the test signal lines by a respective one of the test control transistors. The plurality of test control transistors each have a channel width-to-length ratio between 10 and 200.
Abstract: An antenna structure, a manufacturing method thereof, and a communication device are disclosed. The antenna structure includes a first substrate, a second substrate, a dielectric layer, a plurality of first electrodes and a plurality of second electrodes. The dielectric layer is disposed between the first substrate and the second substrate; the plurality of first electrodes are disposed at intervals on a side of the first substrate adjacent to the dielectric layer; the plurality of second electrodes are disposed at intervals on a side of the second substrate adjacent to the dielectric layer; a side of the first substrate facing the second substrate includes a plurality of first recess portions each including a first concaved surface which is dented into the first substrate; the dielectric layer is at least partly disposed in the plurality of first recess portions.
January 8, 2018
Date of Patent:
December 15, 2020
BOE TECHNOLOGY GROUP CO., LTD.
Yongchun Lu, Xinyin Wu, Hongfei Cheng, Chunping Long
Abstract: A display substrate includes a base substrate and an encapsulation film disposed at a first side of the base substrate. At least one corner of an edge of the encapsulation film is a rounded corner or a substantially rounded corner.
Abstract: An array substrate includes a base substrate, at least one first signal line and at least one second signal line disposed at a first side of the base substrate, and at least one electrostatic discharge (ESD) protection device disposed at the first side of the base substrate. Each ESD protection device includes a first electrode coupled to one first signal line, a second electrode coupled to one second signal line, and an insulating medium disposed between the first electrode and the second electrode. An orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate, and the ESD protection device is configured to discharge electrostatic charges on one of the first signal line and the second signal line that are coupled to the ESD protection device to the other one.
Abstract: The present disclosure discloses a display substrate and a display device. The package structure of the display component includes: a base substrate, a display component arranged on a surface of the base substrate, and a package layer covering the display component, in which the display component includes a display area and a peripheral area surrounding the display area, and the peripheral area is provided with a signal line pattern having an inclined side along a direction perpendicular to an extending direction of the signal line pattern with a slope angle of less than 90 degrees.
Abstract: An array substrate, a fabrication method thereof, and an organic light-emitting diode display device are provided; the array substrate (10) comprises a base substrate (100), the base substrate (100) including a display region (102) and a peripheral region (101) surrounding the display region (102), the display region (102) including: a plurality of data lines (12) and a plurality of gate lines (11) intersecting with each other, a plurality of pixel regions (21), formed in a matrix and defined by the plurality of data lines (12) and the plurality of gate lines (11) intersecting with each other formed on the base substrate (100), wherein a thin film transistor (32) is formed in each of the plurality of pixel regions (21); and further, the array substrate (10) also comprises at least one solar cell unit (31), which, together with the thin film transistor (32), is located on a same side of the base substrate (100), and is formed in at least one of the plurality of pixel regions (21) and the peripheral region (101
Abstract: An array substrate includes: a base substrate; one or more first signal lines provided on the base substrate; a plurality of repair line sets also provided on the base substrate and configured to repair the first signal lines, each of the repair line sets comprising one or more repair lines which intersect with and are insulated from at least one of the first signal lines; and one or more second signal lines also provided on the base substrate, at least one of the one or more second signal lines having one end which is arranged to intersect with and be insulated from the one or more repair lines, and the other end which is connected to a driving circuit for supplying an electrical signal to the one or more first signal lines. The second signal line is different from the first signal line.