Abstract: The present disclosure relates to an array substrate, a display panel, and a display device. The array substrate comprises a display area and a non-display area surrounding the display area; wherein: the display area includes gate lines and data lines, and a plurality of pixel units defined by the intersections of gate lines and data lines, each of the pixel units including a thin film transistor and a pixel electrode electrically connected to a drain electrode of the thin film transistor; the non-display area includes a plurality of dummy pixel units arranged around the display area, each of the dummy pixel units including a dummy thin film transistor and a dummy pixel electrode floating relative to a drain electrode of the dummy thin film transistor; the non-display area further includes a dummy common electrode structure electrically connected to at least some of the dummy pixel units.

Abstract: A preparation delivery assembly includes: a first substrate, a second substrate, and at least two needles of different lengths. Two side walls are provided between the first and second substrates to define a first chamber. At least one first channel that is in communication with the first chamber is provided in the second substrate in a direction perpendicular to the second substrate. And the needles are arranged on a surface of the second substrate, and each needle is in communication with the first chamber to deliver the preparation. A third channel is provided in the first substrate in a direction perpendicular to the first substrate, and one end of the third channel is in communication with the first chamber so as to guide the preparation introduced from the other end of the third channel into the first chamber.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a display region and a non-display region around the display region, and further includes: a first leading wire extending from the non-display region to the display region and a second leading wire extending from the non-display region to the display region. The first leading wire is between a first signal line and a first fan-out line and electrically connects the first signal line and the first fan-out line, and the second leading wire is between a second signal line and a second fan-out line and electrically connects the second signal line and the second fan-out line. The first leading wire and the second leading wire are in different layers.

Abstract: A method for manufacturing an array substrate includes: providing a base substrate; forming gate lines and data lines intercrossing each other, the gate lines and the data lines define multiple pixel units. Multiple pixel regions are formed in each pixel unit, a display electrode having a slit is formed in each pixel region. Each data line includes multiple data line segments. In each pixel unit, each of a part of the pixel regions has a display electrode whose slit is parallel to a data line segment adjacent to this pixel region; each of another part of the pixel regions has a display electrode whose slit is non-parallel to a data line segment adjacent to this pixel region. The display electrodes in each of the pixel units are located at a same side of the gate line to which the pixel unit where the display electrodes are located is coupled.

Abstract: Embodiments of the present disclosure provide a preparation delivery assembly including: a first substrate, a second substrate, and at least two needles of different lengths, each of which is a hollow needle having a hollow structure; wherein two side walls are provided between the first substrate and the second substrate to define a first chamber for containing a preparation by the first substrate, the second substrate, and the two side walls; at least one first channel that is in communication with the first chamber is provided in the second substrate in a direction substantially perpendicular to the second substrate; and the needles are arranged on a surface of the second substrate distal to the first substrate, and each of the needles is in communication with the first chamber through the at least one first channel to deliver the preparation.

Abstract: The present disclosure relates to a driving unit. The driving unit may include a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit may include a plurality of first switching elements, and at least some of the plurality of first switching elements may be configured to output a first signal to a first output terminal of the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit may include one or more second switching elements, and at least one of the one or more second switching elements may be configured to output a second signal to a second output terminal of the driving unit in response to the control signal from the driving control circuit. The driving control circuit may be configured to output the control signal at a control signal output terminal.

Abstract: The present disclosure relates to a driving unit. The driving unit may include a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit may include a plurality of first switching elements, and at least some of the plurality of first switching elements may be configured to output a first signal to a first output terminal of the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit may include one or more second switching elements, and at least one of the one or more second switching elements may be configured to output a second signal to a second output terminal of the driving unit in response to the control signal from the driving control circuit. The driving control circuit may be configured to output the control signal at a control signal output terminal.

Abstract: The present disclosure relates to a driving unit. The driving unit may include a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit may include a plurality of first switching elements, and at least some of the plurality of first switching elements may be configured to output a first signal to a first output terminal of the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit may include one or more second switching elements, and at least one of the one or more second switching elements may be configured to output a second signal to a second output terminal of the driving unit in response to the control signal from the driving control circuit. The driving control circuit may be configured to output the control signal at a control signal output terminal.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a base substrate, and a first functional layer and a second functional layer laminated one on another on the base substrate. The first functional layer forms a level-different region on the base substrate, and the second functional layer covers the level-different region. A portion of the first functional layer at the level-different region is provided with a target gradient angle, the target gradient angle is a maximum gradient angle when the second functional layer has a predetermined thickness, and the predetermined thickness is a thickness when a functional requirement of the second functional layer has been met and the second functional layer is not broken at the level-different region.

Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes a first electrode having a first groove group, a second groove group and a non-hollow portion; the first groove group includes a plurality of hollow first grooves arranged successively, each first groove includes a first end and a second end arranged along an extending direction thereof; the second groove group includes a plurality of hollow second grooves arranged successively, each second groove includes a third end and a fourth end arranged along an extending direction thereof, and a third end is on a side of the fourth end adjacent to the first groove group; and the third end of at least one second groove is staggered with respect to the second end of the first groove adjacent to the third end.

Abstract: An electrostatic protection circuit and a manufacturing method thereof, an array substrate and a display apparatus in the field of display technology are provided. This electrostatic protection circuit includes: a discharge sub-circuit, a buffer sub-circuit and an electrostatic protection line, wherein the electrostatic protection line is a common electrode line; the buffer sub-circuit includes a third transistor and a fourth transistor; a gate and a second electrode of the third transistor are both connected to a first electrode of the fourth transistor, and the first electrode of the third transistor is connected to a signal line; a gate and a second electrode of the fourth transistor are both connected to the signal line.

Abstract: A touch display panel is disclosed, which includes components of a conventional touch display panel, and further includes: first leads and first data lines share a first test signal line, second leads and second data lines share a second test signal line: and first touch test switches for controlling the first leads and first data test switches for controlling the first data lines are not simultaneously turned on, second touch test switches for controlling the second leads and second data test switches for controlling the second data lines are not simultaneously turned on.

Abstract: The present disclosure provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a plurality of pixel units arranged in a matrix, each the pixel unit includes a plurality of pixel regions, each pixel region is provided with a display electrode having a slit; a plurality of data lines, each of the data lines includes a plurality of data line segments, any two adjacent data line segments are electrically coupled to each other; in each of the pixel units, each of a part of the pixel regions has a display electrode whose slit is parallel to a data line segment adjacent to this display electrode in the data lines; each of another part of the pixel regions has a display electrode whose slit is non-parallel to a data line segment adjacent to this display electrode in the data lines.

Abstract: Provided are an array substrate and a display panel. The array substrate includes: gate lines and data lines on a substrate, the gate lines extending in a first direction, the data lines extending in a second direction, and the gate lines and the data lines crossing over each other to define pixel regions arranged in a matrix; pixel electrodes respectively in the plurality of pixel regions and on a side of the gate lines away from the substrate; common electrode lines at least partially surrounding the plurality of pixel regions; and a shielding electrode on a side of the gate lines away from the substrate and electrically connected to the common electrode lines, an orthographic projection of the shielding electrode on the substrate covering an orthographic projection of a portion, between the pixel electrodes adjacent in the second direction, of at least one of the gate lines on the substrate.

Abstract: An array substrate includes a base substrate, at least one first signal line and at least one second signal line disposed at a first side of the base substrate, and at least one electrostatic discharge (ESD) protection device disposed at the first side of the base substrate. Each ESD protection device includes a first electrode coupled to one first signal line, a second electrode coupled to one second signal line, and an insulating medium disposed between the first electrode and the second electrode. An orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate, and the ESD protection device is configured to discharge electrostatic charges on one of the first signal line and the second signal line that are coupled to the ESD protection device to the other one.

Abstract: Provided are an array substrate and a method for manufacturing the same, a display device and a method for manufacturing the same. In the array substrate, the drain of the thin film transistor is extended to form a drain extension line, wherein the drain extension line is between adjacent sub-pixel units of the pixel region, thus it can block the light at the boundary between the sub-pixel units, thereby avoiding light leakage duo to the disordered electric field at the boundary between the sub-pixel units. The array substrate of the present disclosure is suitable for a multi-domain oriented IPS mode array substrate. The drain extension line can be used as a light blocking strip to prevent light leakage due to the disordered electric field at the boundary between the sub-pixels, and is overlapped with the middle portion of the common electrode line to form a storage capacitor.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a base substrate, and a first functional layer and a second functional layer laminated one on another on the base substrate. The first functional layer forms a level-different region on the base substrate, and the second functional layer covers the level-different region. A portion of the first functional layer at the level-different region is provided with a target gradient angle, the target gradient angle is a maximum gradient angle when the second functional layer has a predetermined thickness, and the predetermined thickness is a thickness when a functional requirement of the second functional layer has been met and the second functional layer is not broken at the level-different region.

Abstract: The present disclosure provides a thin film transistor, a display panel and a method for manufacturing the thin film transistor. The thin film transistor includes an active layer and a source-drain electrode layer, the source-drain electrode layer includes a first electrode having at least one first electrode strip and a second electrode having at least one second electrode strip, the at least one first electrode strip and the at least one second electrode strip are alternately arranged at intervals, and at least an insulating part of a layer where the active layer is located is provided with an insulating material, and the insulating part is located at an orthographic projection of at least a part of a region between a free end of the first electrode strip, which is proximal to the second electrode, and the second electrode, on the layer where the active layer is located.

Abstract: An electrostatic protection circuit and a manufacturing method, an array substrate and a display apparatus in field of display technologies are provided. The electrostatic protection includes a first thin film transistor, a second thin film transistor, and an electrostatic protection line; a gate and a second electrode of the first thin film transistor are connected to a signal line, and a first electrode of the first thin film transistor is connected to the electrostatic protection line; a gate and a second electrode of the second thin film transistor are connected to the electrostatic protection line, and a first electrode of the second thin film transistor is connected to the signal line; each thin film transistor is an oxide thin film transistor, a length-width ratio of a channel of each thin film transistor is greater than or equal to a length-width ratio threshold, the length-width ratio threshold being 5.

Abstract: The present disclosure provides a display substrate, a fabrication method thereof and a display panel. The display substrate includes a display area (101) and a non-display area (102) around the display area (101), the display substrate further includes: a base substrate (100); at least one barrier dam (200) and a first encapsulating layer (310) on the base substrate (100), the barrier dam (200) is in the non-display area (102) on the base substrate (100), the first encapsulating layer (310) is on the base substrate (100) and on a side of the at least one barrier dam (200) facing the display area (101), the first encapsulating layer (310) is formed by a first encapsulating material (301) in a cured state, and at least a side of the barrier dam (200) facing the first encapsulating layer (310) is lyophobic with respect to the first encapsulating material (301) in a non-cured state.