Patents by Inventor Chunsheng Jiang
Chunsheng Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10991724Abstract: The present disclosure provides a CMOS transistor and a method for fabricating the same, a display panel and a display device. The method includes: forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, wherein a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.Type: GrantFiled: December 20, 2018Date of Patent: April 27, 2021Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Chunsheng Jiang
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Patent number: 10811444Abstract: The present application provides a method for fabricating a back channel etching oxide semiconductor TFT substrate, by depositing the first passivation layer on the source, the drain and the active layer, and treating the oxygen element containing plasma to a surface of the first passivation layer, infiltrating traces of oxygen element into the superficial layer of the channel region of the active layer through the first passivation layer, then using an oxygen element containing plasma to treat the surface of the first passivation layer, so that the traces of oxygen element infiltrates into the superficial layer of the channel region of the active layer via the first passivation layer, to supply the oxygen element to the superficial layer of the channel region, and ensure the oxygen element balance in the superficial layer, the first passivation layer acts as a barrier layer to ensure the stability of the TFT.Type: GrantFiled: December 14, 2017Date of Patent: October 20, 2020Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Chunsheng Jiang
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Patent number: 10727322Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method uses low deposition power and low oxygen content to deposit first silicon oxide thin film; then increases deposition power with low oxygen content to deposit second silicon oxide thin film. The first and second silicon oxide thin films form a passivation layer; the second silicon oxide film is implanted with oxygen to form a superficial layer so that the Si:O atomic ratio in the superficial layer is close to or same as Si:O atomic ratio of SiO2, to ensure the passivation layer in contact with the air side is strongly hydrophobic to prevent outside water vapor into the back-channel, while ensuring the side of passivation layer contacting IGZO active layer has a lower oxygen content to reduce the probability of forming unbalanced O-ions at the interface between passivation layer and IGZO active layer.Type: GrantFiled: May 14, 2019Date of Patent: July 28, 2020Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Chunsheng Jiang
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Patent number: 10714514Abstract: A BCE TFT substrate includes a base substrate. A gate and a gate insulation layer are sequentially formed on the base substrate. An IGZO semiconductor layer is formed on the gate insulation layer to serve as an active layer. A source and a drain are disposed on the active layer and spaced from each other. Each of the source and drain is formed of a Mo layer, a Cu layer, and a conductorized IGZO film that are sequentially stacked on the active layer. A passivation layer is disposed on the source, the drain, and the active layer.Type: GrantFiled: July 2, 2019Date of Patent: July 14, 2020Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Chunsheng Jiang
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Publication number: 20200152672Abstract: The present application provides a method for fabricating a back channel etching oxide semiconductor TFT substrate, by depositing the first passivation layer on the source, the drain and the active layer, and treating the oxygen element containing plasma to a surface of the first passivation layer, infiltrating traces of oxygen element into the superficial layer of the channel region of the active layer through the first passivation layer, then using an oxygen element containing plasma to treat the surface of the first passivation layer, so that the traces of oxygen element infiltrates into the superficial layer of the channel region of the active layer via the first passivation layer, to supply the oxygen element to the superficial layer of the channel region, and ensure the oxygen element balance in the superficial layer, the first passivation layer acts as a barrier layer to ensure the stability of the TFT.Type: ApplicationFiled: December 14, 2017Publication date: May 14, 2020Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Cp., Ltd.Inventor: Chunsheng JIANG
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Patent number: 10510779Abstract: The present disclose provides in some embodiments an array substrate and a method for fabricating the same, and a display device. The array substrate includes a source-drain metal layer formed on a base substrate and including copper, an alloy layer formed on the source-drain metal layer and including copper alloy, non-copper metal in the copper alloy being easier to be oxidized than copper in the copper alloy, a passivation layer formed on the alloy layer, and an oxide layer formed between the alloy layer and the passivation layer.Type: GrantFiled: March 3, 2016Date of Patent: December 17, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Chunsheng Jiang
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Publication number: 20190326337Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The manufacturing method of BCE TFT substrate of the invention comprises disposing the surface layer of the source and drain as a conductorized IGZO film. Because the bonding between the conductorized IGZO film and the silicon oxide is strong, the passivation layer is prevented from curling up and forming bubbles. Moreover, in the process to form the source and drain the fluorine-free etching solution is used to remove the source-drain spacer, causing no damage to the channel region of the active layer. In the BCE TFT substrate of the invention, the surface layer of the source and drain is disposed as a conductorized IGZO film. Because the bonding between the conductorized IGZO film and the silicon oxide is strong, the passivation layer is prevented from curling up and forming bubbles.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventor: Chunsheng Jiang
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Patent number: 10453874Abstract: A manufacturing method for an array substrate is provided. The manufacturing method includes steps of: forming a first metal layer, a gate electrode layer, a gate electrode insulated layer, a semiconductor layer, a second metal layer, a source electrode layer, and a drain electrode layer on a base substrate in order. The step of forming the gate electrode layer on the first metal layer further includes steps of: depositing a gate electrode metal layer; exposing, developing, and wet etching on the gate electrode metal layer; and removing a photoresist layer. Metal cations are added into a stripper liquid, an electrochemical corrosion potential of which is less than that of the first metal layer, so as to avoid a short line problem.Type: GrantFiled: November 28, 2017Date of Patent: October 22, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventors: Chunsheng Jiang, Yue Wu
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Publication number: 20190267476Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method comprises forming a first IGZO thin film with polycrystalline IGZO particles in a predetermined area of active layer before sputtering IGZO, the polycrystalline IGZO particles in the first IGZO thin film used as seed crystal during sputtering to grow a C-axis crystallized IGZO in good crystalline state to form a second IGZO thin film. The first and second IGZO thin films form an active layer. Because the surface of the active layer is presented as C-axis crystallized IGZO, the active layer is not damaged by the copper etchant during etching source and drain so as to ensure stable performance of active layer and to avoid the development of special copper etching solution. As such, the BCE TFT substrate has stable electrical performance. The BCE TFT substrate manufactured by the above manufacturing method has stable electrical performance.Type: ApplicationFiled: May 10, 2019Publication date: August 29, 2019Inventor: Chunsheng Jiang
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Publication number: 20190267477Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method uses low deposition power and low oxygen content to deposit first silicon oxide thin film; then increases deposition power with low oxygen content to deposit second silicon oxide thin film. The first and second silicon oxide thin films form a passivation layer; the second silicon oxide film is implanted with oxygen to form a superficial layer so that the Si:O atomic ratio in the superficial layer is close to or same as Si:O atomic ratio of SiO2, to ensure the passivation layer in contact with the air side is strongly hydrophobic to prevent outside water vapor into the back-channel, while ensuring the side of passivation layer contacting IGZO active layer has a lower oxygen content to reduce the probability of forming unbalanced O-ions at the interface between passivation layer and IGZO active layer.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventor: Chunsheng Jiang
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Patent number: 10355035Abstract: A manufacturing method of the back-channel-etched (BCE) TFT substrate, able to prevent the passivation layer from curling up and forming bubbles, while not causing damaging to the channel region of the active layer.Type: GrantFiled: December 20, 2017Date of Patent: July 16, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Chunsheng Jiang
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Patent number: 10332988Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method uses low deposition power and low oxygen content to deposit first silicon oxide thin film; then increases deposition power with low oxygen content to deposit second silicon oxide thin film. The first and second silicon oxide thin films form a passivation layer; the second silicon oxide film is implanted with oxygen to form a superficial layer so that the Si:O atomic ratio in the superficial layer is close to or same as Si:O atomic ratio of SiO2, to ensure the passivation layer in contact with the air side is strongly hydrophobic to prevent outside water vapor into the back-channel, while ensuring the side of passivation layer contacting IGZO active layer has a lower oxygen content to reduce the probability of forming unbalanced O-ions at the interface between passivation layer and IGZO active layer.Type: GrantFiled: December 20, 2017Date of Patent: June 25, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Chunsheng Jiang
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Patent number: 10332989Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method comprises forming a first IGZO thin film with polycrystalline IGZO particles in a predetermined area of active layer before sputtering IGZO, the polycrystalline IGZO particles in the first IGZO thin film used as seed crystal during sputtering to grow a C-axis crystallized IGZO in good crystalline state to form a second IGZO thin film. The first and second IGZO thin films form an active layer. Because the surface of the active layer is presented as C-axis crystallized IGZO, the active layer is not damaged by the copper etchant during etching source and drain so as to ensure stable performance of active layer and to avoid the development of special copper etching solution. As such, the BCE TFT substrate has stable electrical performance. The BCE TFT substrate manufactured by the above manufacturing method has stable electrical performance.Type: GrantFiled: December 20, 2017Date of Patent: June 25, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Chunsheng Jiang
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Publication number: 20190157430Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method uses low deposition power and low oxygen content to deposit first silicon oxide thin film; then increases deposition power with low oxygen content to deposit second silicon oxide thin film. The first and second silicon oxide thin films form a passivation layer; the second silicon oxide film is implanted with oxygen to form a superficial layer so that the Si:O atomic ratio in the superficial layer is close to or same as Si:O atomic ratio of SiO2, to ensure the passivation layer in contact with the air side is strongly hydrophobic to prevent outside water vapor into the back-channel, while ensuring the side of passivation layer contacting IGZO active layer has a lower oxygen content to reduce the probability of forming unbalanced O-ions at the interface between passivation layer and IGZO active layer.Type: ApplicationFiled: December 20, 2017Publication date: May 23, 2019Inventor: Chunsheng Jiang
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Publication number: 20190157318Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The manufacturing method of BCE TFT substrate of the invention comprises disposing the surface layer of the source and drain as a conductorized IGZO film. Because the bonding between the conductorized IGZO film and the silicon oxide is strong, the passivation layer is prevented from curling up and forming bubbles. Moreover, in the process to form the source and drain the fluorine-free etching solution is used to remove the source-drain spacer, causing no damage to the channel region of the active layer. In the BCE TFT substrate of the invention, the surface layer of the source and drain is disposed as a conductorized IGZO film. Because the bonding between the conductorized IGZO film and the silicon oxide is strong, the passivation layer is prevented from curling up and forming bubbles.Type: ApplicationFiled: December 20, 2017Publication date: May 23, 2019Inventor: Chunsheng Jiang
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Publication number: 20190157429Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The manufacturing method of BCE TFT substrate of the invention uses C-axis crystallized IGZO thin film to fabricate the active layer. Because the C-axis crystallized IGZO has extremely high corrosion resistance and is resistant to the erosion of the copper etchant, the active layer is not damaged in the source/drain etching process, and the performance of the active layer is stable. The manufactured BCE TFT substrate has stable electric performance. The amorphous IGZO thin film for fabricating the C-axis crystallized IGZO thin film is prepared under high oxygen atmosphere, so that the crystallization annealing temperature of the amorphous IGZO thin film is reduced to 600° C. or below. A high-temperature annealing furnace is saved and the production cost reduced. The BCE TFT substrate of the invention manufactured by the above method has stable electric performance and low production cost.Type: ApplicationFiled: December 20, 2017Publication date: May 23, 2019Inventor: Chunsheng Jiang
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Publication number: 20190157431Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method comprises forming a first IGZO thin film with polycrystalline IGZO particles in a predetermined area of active layer before sputtering IGZO, the polycrystalline IGZO particles in the first IGZO thin film used as seed crystal during sputtering to grow a C-axis crystallized IGZO in good crystalline state to form a second IGZO thin film. The first and second IGZO thin films form an active layer. Because the surface of the active layer is presented as C-axis crystallized IGZO, the active layer is not damaged by the copper etchant during etching source and drain so as to ensure stable performance of active layer and to avoid the development of special copper etching solution. As such, the BCE TFT substrate has stable electrical performance. The BCE TFT substrate manufactured by the above manufacturing method has stable electrical performance.Type: ApplicationFiled: December 20, 2017Publication date: May 23, 2019Inventor: Chunsheng Jiang
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Publication number: 20190144748Abstract: A Cu—MoTi etching solution is provided. The Cu—MoTi etching solution includes 5 to 30 wt % of an oxidant, 3 to 15 wt % of an acid, 3 to 15 wt % of an inorganic salt, and the balance deionized water. The oxidant is selected from hydrogen peroxide or persulfuric acid. The acid is selected from polycarboxylic acids, amino acids, or inorganic acids. The inorganic salt is selected from diammonium hydrogen phosphate or ammonium dihydrogen phosphate.Type: ApplicationFiled: November 24, 2017Publication date: May 16, 2019Inventors: Yue WU, Shan Li, Chunsheng JIANG, Chia-Yu Lee
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Publication number: 20190123070Abstract: The present disclosure provides a CMOS transistor and a method for fabricating the same, a display panel and a display device. The method includes: forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, wherein a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventor: Chunsheng JIANG
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Patent number: 10256315Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The thin film transistor comprises a copper gate, a gate insulating layer, an active layer, a source, and a drain. The thin film transistor further comprises a copper alloy layer which is arranged on a side of the gate facing the active layer.Type: GrantFiled: March 7, 2016Date of Patent: April 9, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Chunsheng Jiang, Xuyuan Li, Wei Liu, Xiaming Zhu