Patents by Inventor Chyu-Jiuh Torng

Chyu-Jiuh Torng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733039
    Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu, Wenhan Zhang, Hualiang Yu
  • Publication number: 20200201697
    Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. LIU, Wenhan Zhang, Hualiang Yu
  • Publication number: 20200193280
    Abstract: This disclosure relates to artificial intelligence (AI) circuits with embedded memory for storing trained AI model parameters. The embedded memory cell structure, device profile, and/or fabrication process are designed to generate binary data access asymmetry and error rate asymmetry between writing binary zeros and binary ones that are adapted to and compatible with a binary data asymmetry of the trained model parameters and/or a bit-inversion tolerance asymmetry of the AI model between binary zeros and ones. The disclosed method and system improves predictive accuracy and memory error tolerance without significantly reducing an overall memory error rate and without relying on memory cell redundancy and error correction codes.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Hualiang Yu, Wenhan Zhang, Daniel H. Liu
  • Patent number: 10672455
    Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 2, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. Liu
  • Patent number: 10592804
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 17, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Publication number: 20200042888
    Abstract: This disclosure relates to a self-contained and self-sufficient edge device capable of performing processing data sets using a convolutional neural network model without relying on any backend servers. In particularly, the edge device may include non-volatile memory cells for storing a full set of trained model parameters from the convolutional neural network model. The non-volatile memory cells may be based on magnetic random access memory cells and may be embedded on the same semiconductor substrate with a convolutional neural network logic circuit dedicated to parallel forward propagation calculation.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Hualiang YU, Chyu-Jiuh Torng, Daniel H. Liu
  • Patent number: 10552733
    Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) element.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 4, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel Liu
  • Patent number: 10545693
    Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: January 28, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10546234
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. A first CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem, which includes a first one-time-programming (OTP) memory for filter coefficients and a second memory for imagery data. A second CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem that includes a first memory for filter coefficients, a second memory for imagery data and a third OTP memory for unique data pattern (e.g., security purpose). Either STT-RAM or OST-MRAM can be configured as different memories of the memory subsystem.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: January 28, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10534996
    Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights or filter coefficients. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a voltage-controlled magnetic anisotropy (VCMA) based magnetic tunnel junction (MTJ) element. Magnetization direction in VCMA based MTJ element can be in-plane or out-of-plane.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 14, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel Liu
  • Publication number: 20190363131
    Abstract: This disclosure relates to embedding memories into with logic circuits for improving memory access speed and reducing power consumption. In particular, memories of distinct types embedded with logic circuits on a same semiconductor substrate are disclosed. These memories may include static random access memory, magnetoresistive random access memory, and various types of resistive random access memory. These different types of memories may be combined to form an embedded memory subsystem that provide distinct memory persistency, programmability, and access characteristics tailored for storing different type of data in, e.g., application involving convolutional neural networks.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu
  • Patent number: 10481815
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 19, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Publication number: 20190267072
    Abstract: An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. LIU
  • Publication number: 20190258923
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Publication number: 20190258416
    Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Publication number: 20190258417
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10347317
    Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. Liu
  • Patent number: 10331367
    Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first memory and second memory. The first memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 25, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10331368
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 25, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10331999
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 25, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong