Abstract: A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract: A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract: A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

Abstract: A method of controlling a discharge of bit lines of a matrix of memory cells comprises conditioning a value of a current flowing through a bit line of the matrix during a bit line discharge phase to an absence of an indication of defectiveness of the bit line. The method allows preventing crowbar currents that otherwise flow during the bit line discharge phase when a defective bit line exhibits a short-circuit to a defective word line.

Abstract: A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to receive a supply voltage, a second input coupled to receive a reference voltage, and an output coupled to one of the row decoder and the column decoder to supply the first biasing voltage. A second voltage booster has a first input coupled to receive the supply voltage, a second input coupled to the output of the first voltage booster to receive the first biasing voltage, and an output coupled to the other of the row decoder and the column decoder to supply the second biasing voltage.

Abstract: A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

Abstract: A memory device is proposed.

Abstract: A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.

Abstract: A phase change memory device includes a plurality of phase-change memory cells, arranged in rows and columns, phase-change memory cells arranged on the same column being connected to a same bit line; a plurality of first selectors, each coupled to a respective phase-change memory cell; an addressing circuit for selectively addressing at least one of the bit lines, one of the first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector; and a regulated voltage supply circuit, selectively connectable to the addressed bit line, for supplying a bit line voltage. The bit line voltage is correlated to a first control voltage on the addressed first selector, coupled to the addressed phase-change memory cell.

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract: A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to receive a supply voltage, a second input coupled to receive a reference voltage, and an output coupled to one of the row decoder and the column decoder to supply the first biasing voltage. A second voltage booster has a first input coupled to receive the supply voltage, a second input coupled to the output of the first voltage booster to receive the first biasing voltage, and an output coupled to the other of the row decoder and the column decoder to supply the second biasing voltage.