Patents by Inventor Clive Bittlestone

Clive Bittlestone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170047130
    Abstract: Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.
    Type: Application
    Filed: August 12, 2015
    Publication date: February 16, 2017
    Inventors: Yuming Zhu, Manish Goel, Clive Bittlestone, Yunchen Qiu, Sai Zhang
  • Publication number: 20170046090
    Abstract: A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.
    Type: Application
    Filed: August 13, 2015
    Publication date: February 16, 2017
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuming Zhu, Manish Goel, Clive Bittlestone
  • Publication number: 20170038807
    Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.
    Type: Application
    Filed: August 3, 2015
    Publication date: February 9, 2017
    Inventors: Clive BITTLESTONE, Joyce KWONG, Manish GOEL
  • Publication number: 20170017808
    Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
    Type: Application
    Filed: July 13, 2015
    Publication date: January 19, 2017
    Inventors: Joyce KWONG, Clive BITTLESTONE, Manish GOEL
  • Publication number: 20170011790
    Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.
    Type: Application
    Filed: July 8, 2015
    Publication date: January 12, 2017
    Inventors: Chiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy
  • Publication number: 20160365510
    Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 15, 2016
    Inventors: Chiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy, Stephen Heinrich-Barna
  • Publication number: 20160342471
    Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 24, 2016
    Inventors: Sai Zhang, Yuming Zhu, Clive Bittlestone, Srinath Ramaswamy
  • Publication number: 20160328289
    Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Only Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.
    Type: Application
    Filed: May 4, 2015
    Publication date: November 10, 2016
    Inventors: Sai Zhang, Yuming Zhu, Clive Bittlestone, Srinath Ramaswamy
  • Patent number: 9453867
    Abstract: A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 27, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Dabak, Clive Bittlestone
  • Patent number: 9401196
    Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy, Stephen K. Heinrich-Barna
  • Publication number: 20150262569
    Abstract: A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: ANAND DABAK, CLIVE BITTLESTONE
  • Publication number: 20140305215
    Abstract: A flow meter ultrasonically measures fluid velocity in a pipe and ultrasonically transmits fluid flow data along the pipe. An ultrasonic transducer used for fluid velocity measurement may optionally also be used for communication of flow data, and optionally, the ultrasonic frequency for fluid velocity measurement may be the same as the ultrasonic frequency for communication of flow data.
    Type: Application
    Filed: April 10, 2013
    Publication date: October 16, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Anand Dabak, Clive Bittlestone
  • Patent number: 7564077
    Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: July 21, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
  • Publication number: 20070290270
    Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
    Type: Application
    Filed: May 7, 2007
    Publication date: December 20, 2007
    Inventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
  • Patent number: 6909301
    Abstract: An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: June 21, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Steven P. Korson, Brian D. Borchers, Bryan Sheffield, Clive Bittlestone, Doug Counce
  • Publication number: 20040218459
    Abstract: An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 4, 2004
    Inventors: Steven P. Korson, Brian D. Borchers, Bryan Sheffield, Clive Bittlestone, Doug Counce
  • Patent number: 6781411
    Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Donald E. Steiss, Clive Bittlestone, Peter Cumming, Christopher Barr
  • Patent number: 6734743
    Abstract: An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a device under test 1. The programmable delay 8 increases the frequency of the clock signal to the device under test 1 until the device under test fails. The cycle time measurement of the device under test 1 is the period of maximum frequency at which the device under test 1 operates properly.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Steven P. Korson, Brian D. Borchers, Bryan Sheffield, Clive Bittlestone, Doug Counce
  • Publication number: 20040046615
    Abstract: An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a device under test 1. The programmable delay 8 increases the frequency of the clock signal to the device under test 1 until the device under test fails. The cycle time measurement of the device under test 1 is the period of maximum frequency at which the device under test 1 operates properly.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Inventors: Steven P. Korson, Brian D. Borchers, Bryan Sheffield, Clive Bittlestone, Doug Counce
  • Publication number: 20040049711
    Abstract: An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Inventors: Steven P. Korson, Brian D. Borchers, Bryan Sheffield, Clive Bittlestone, Doug Counce