Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.

Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on interconnect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.

Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.

Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.

Abstract: A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal.

Abstract: A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.

Abstract: An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of clock signals, thus greatly improving the data rate without increasing the storage rate of the plurality of data storage elements 22a-22d.