Abstract: Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.

Abstract: Disclosed herein is an interconnect structure, including: a dielectric material layer having a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than or equal to about 2.5; a diffusion barrier liner layer disposed in the cavity on the dielectric material; an optional crystallization seed layer disposed on the diffusion barrier liner layer; and a conductive material disposed on the crystallization seed layer when present and filling the opening. When the crystallization seed layer is not present the conductive material is disposed on the diffusion barrier liner.

Abstract: Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.

Abstract: A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

Abstract: A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

Abstract: A structure to detect changes in the integrity of vertical electrical connection structures including a semiconductor layer and an electrically conductive material extending through an entire depth of the semiconductor layer. The electrically conductive material has a geometry that encloses a pedestal portion of the semiconductor layer within an interior perimeter of the electrically conductive material. At least one semiconductor device is present on the pedestal portion of the semiconductor layer within the perimeter of the electrically conductive material.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

Abstract: A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure that includes two dielectric layers. The first dielectric layer has an embedded electrically conductive structure. A second dielectric layer is located above the first dielectric layer. The second dielectric layer and the first dielectric layer have a segment of a dielectric capping layer and a segment of a metal capping layer located between them. The segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer. The segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure. The method includes forming an opening in the second dielectric layer and the metal capping layer that exposes at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer.

Abstract: A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

Abstract: A structure to detect changes in the integrity of vertical electrical connection structures including a semiconductor layer and an electrically conductive material extending through an entire depth of the semiconductor layer. The electrically conductive material has a geometry that encloses a pedestal portion of the semiconductor layer within an interior perimeter of the electrically conductive material. At least one semiconductor device is present on the pedestal portion of the semiconductor layer within the perimeter of the electrically conductive material.

Abstract: The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

Abstract: A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.