Abstract: An image sensor package is disclosed that reduces the overall size of known image sensor packages. The image sensor package includes an image sensor and image sensor controller that are arranged on a substrate so that the surfaces of the image sensor and image sensor controller are directly adjacent one another. A package in accordance with the present invention reduces the amount of space in the package by allowing at least one surface of the image sensor controller and at least one surface of the image sensor to be directly attached or connected to one another. Electrical conductive material in the nature of anisotropic conductive materials is also preferably applied to the substrate in the form of an adhesive layer to allow for the image sensor controller and the image sensor to be in electrical communication with one another.

Abstract: A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.

Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.

Abstract: A method of preparing an optical brightener/PVOH aqueous concentrate comprising the sequential steps of: (a) providing an aqueous brightener composition including water and optical brightener active ingredient, wherein the optical brightener active ingredient is typically present in the aqueous brightener composition in an amount of from about 10% to about 25%; (b) admixing a polyvinyl alcohol resin with said aqueous optical brightener composition in an amount of about 1 part of dry polyvinyl alcohol resin per 0.5 to 10 wet parts of aqueous brightener composition to provide a nascent aqueous concentrate of polyvinyl alcohol resin and optical brightener; and (c) cooking the aqueous concentrate to dissolve the solids typically at a temperature of from about 175° F. to about 210° F. for a time of from about 10 minutes to about 120 minutes to provide a cooked brightener/polyvinyl alcohol concentrate.

Abstract: The present invention relates generally to an improved method of preparing aqueous coating compositions including an optical brightener and a polyvinyl alcohol resin, the improvement being directed to cooking a slurry to dissolve the polyvinyl alcohol resin subsequent to the addition of optical brightener and polyvinyl alcohol resin to the slurry at a temperature above about 160° F. for at least about 5 minutes. The invention enables preparation with lower water content without compromising brightness and color. Particularly preferred is the addition of dry resin and/or dry brightener to provide high solids mixtures. Another aspect of the invention is a dry, particulate blend of brightener and PVOH resin.

Abstract: A component incorporating a dielectric element such as a polymeric film with leads and terminals thereon is assembled with a semiconductor chip and bond regions of the leads are connected to contacts of the chip. At least one lead incorporates a plural set of connecting regions connecting the bond region of that lead to a plurality of terminals. One or more of the connecting regions in each such plural set are severed so as to leave less than all of the terminals associated with each such plural set connected to the contacts of the chip.

Abstract: Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.

Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure such as a flexible dielectric sheet having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. A platen is provided in engagement with a second surface of the first support structure. The first surface of a second support structure, such as a semiconductor wafer, is abutted against the porous layer and, after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may be at least partially cured.

Abstract: The present invention provides a method for fabricating a compliant microelectronic device package and an associated apparatus for substantially obviating thermal, compliancy and interconnection problems. Flexible, dielectric layers are used having on a first surface a plurality conductive leads which are each electrically coupled at a first end to at least one conductive pad also coupled to the first surface of the dielectric layers. A second end of the conductive leads are further coupled between the dielectric layers across a bonding gap. A compliant layer is then coupled to the bottom surface of the dielectric layers. One of the dielectric layers is coupled to the surface of a die by one of the compliant layer such that the die bond pads are juxtaposed with respective leads in the bonding gap. This assembly is attached to a protective structure and is encapsulated. A solder mask may be placed over the exposed surface of the dielectric layers to cover the leads and prevent shoring.

Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.

Abstract: A method for making a semiconductor chip package. At least one compliant pad is provided on a surface of a substrate and a chip unit is attached to the at least one compliant pad. The at least one compliant pad has a first coefficient of thermal expansion (“CTE”). An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed around the at least one compliant pad to form a composite layer between the chip unit and the substrate.

Abstract: Semiconductor chip packages and methods of fabricating the same. The package includes a thermally conductive protective structure having an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure. A chip is disposed in the indentation so that the front surface of the chip, with contacts thereon, faces toward the front of the structure. A flexible dielectric film having terminals thereon is placed on the flange surface, and a compliant material is disposed between the film and the flange surface. The terminals on the film are connected to the contacts on the chip. The individual terminals on the film are movable with respect to the protective structure, which facilitates mounting and compensation for thermal expansion.

Abstract: A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.

Abstract: A semiconductor chip packaging assembly comprising a frame having a central aperture, a flexible substrate attached to the frame across the central aperture, and a unitary support structure having a plurality of apertures therethrough attached to the substrate within the central aperture of the frame with at least some of the substrate terminals underlying the unitary support structure. A chip is disposed within each aperture and attached to the substrate with the electrical contacts of the chip connected to the substrate terminals. A compliant layer is disposed between the substrate and the unitary support structure and between the substrate and the chip.

Abstract: Filled, curable siloxane encapsulant compositions containing a curable siloxane base resin with functional groups reactive with functional groups of a hardener compound to form a polysiloxane, and filler particles with surface functional groups reactive with the hardener compound functional groups, wherein the filler particles have at least a bi-modal particle packing distribution of first filler particles having a first diameter and second filler particles having a second diameter smaller than the first diameter, and the first and second filler particles are present in amounts effective to provide a particle packing distribution with a relative bulk volume of at least about 90 percent.

Abstract: A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. The leads interconnect contacts on the chip to the terminals on the substrate wherein at least some of the terminals lie outside the periphery of the chip. Typically, the spacer layer is comprised of a compliant or resilient material. A curable encapsulant material is deposited so as to encapsulate the leads and at least one surface of the chip. A unitary support structure is then aligned and attached to the encapsulant around the edges of the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.

Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.

Abstract: A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion (“CTE”) and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip.