Patents by Inventor Craig Mitchell

Craig Mitchell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6133639
    Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: October 17, 2000
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas H. Distefano, John W. Smith
  • Patent number: 6045655
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: April 4, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 5932254
    Abstract: A fixture for encapsulating microelectronic devices includes a structure defining a device-receiving pocket and a well communicating with the pocket so that the passage and well define an interior space whereby the pocket is disposed above the well when the structure is in a first orientation and the well is disposed above the pocket when the structure is in a second orientation. The fixture also includes an element for sealing the interior space and a port for connecting the sealed interior space to an evacuation device.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 3, 1999
    Assignee: Tessera, Inc.
    Inventors: Craig Mitchell, Thomas H. Distefano
  • Patent number: 5929517
    Abstract: Semiconductor chip packages and methods of fabricating the same. The package includes a thermally conductive protective structure having an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure. A chip is disposed in the indentation so that the front surface of the chip, with contacts thereon, faces toward the front of the structure. A flexible dielectric film having terminals thereon is placed on the flange surface, and a compliant material is disposed between the film and the flange surface. The terminals on the film are connected to the contacts on the chip. The individual terminals on the film are movable with respect to the protective structure, which facilitates mounting and compensation for thermal expansion.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: July 27, 1999
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Konstantine Karavakis, Craig Mitchell, John W. Smith
  • Patent number: 5875545
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: March 2, 1999
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 5766987
    Abstract: Microelectronic assemblies such as semiconductor chip assemblies are encapsulated. During encapsulation, the terminals carried by a dielectric layer in each assembly, and the bottom surface of the semiconductor chip in each assembly are protected by covering layers. The covering layers confine the liquid encapsulant and prevent contamination of the terminals and chip bottom surfaces. The encapsulation process may be conducted by using a tilting fixture. The liquid encapsulant and the assemblies are placed into the fixture, the fixture is closed and evacuated, and the encapsulant is then poured onto the assemblies while maintaining the fixture under vacuum. The fixture is then pressurized and maintained under pressure during cure of the encapsulant.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: June 16, 1998
    Assignee: Tessera, Inc.
    Inventors: Craig Mitchell, Thomas H. Distefano
  • Patent number: 5663106
    Abstract: A method of packaging a semiconductor chip assembly includes the encapsulation of the same after establishing an encapsulation area and providing a physical barrier for protecting the terminals of a chip carrier. An alternative or supplement to providing a physical barrier is to provide a preform of an encapsulation material which includes a predetermined volume of such material so that only the encapsulation area is filled. For a semiconductor chip assembly which does not yet have an elastomeric layer, a method of simultaneously forming such an elastomeric layer and encapsulating a semiconductor chip assembly is also provided.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: September 2, 1997
    Assignee: Tessera, Inc.
    Inventors: Konstantine Karavakis, Thomas H. Distefano, John W. Smith, Jr., Craig Mitchell
  • Patent number: 5659952
    Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: August 26, 1997
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas H. Distefano, John W. Smith
  • Patent number: 5548091
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: August 20, 1996
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell