Patents by Inventor Cyprian Emeka Uzoh

Cyprian Emeka Uzoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190319007
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 17, 2019
    Inventors: Cyprian Emeka UZOH, Jeremy Alfred THEIL, Liang WANG, Rajesh KATKAR, Guilian GAO, Laura Wills MIRKARIMI
  • Patent number: 10446441
    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 15, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10446532
    Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, Jr.
  • Patent number: 10440822
    Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130?) covered by a conductive coating (130?) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 8, 2019
    Assignee: Invensas Corporation
    Inventors: Bong-Sub Lee, Cyprian Emeka Uzoh, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram
  • Publication number: 20190304904
    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Zhuowen Sun
  • Patent number: 10418338
    Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 17, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10410977
    Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: September 10, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 10396114
    Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 27, 2019
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Terrence Caskey
  • Publication number: 20190252364
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 15, 2019
    Inventors: Cyprian Emeka UZOH, Laura Wills MIRKARIMI, Guilian GAO, Gaius Gillman FOUNTAIN, JR.
  • Patent number: 10332854
    Abstract: A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 25, 2019
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Gabriel Z. Guevara, Xuan Li, Cyprian Emeka Uzoh, Guilian Gao, Liang Wang
  • Patent number: 10332833
    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 25, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Zhuowen Sun
  • Patent number: 10333014
    Abstract: Methods of and apparatuses for making a photovoltaic cell are provided. The photovoltaic cell is able to have a substrate made of a composite material. The composite material is able to be formed by mixing a binder and a physical property enhancing material to form a mixer. The binder is able to be pitch, such as mesophase pitch. The physical property enhancing material is able to be fiber glass. The substrate of the photovoltaic cell is able to be flexible, such that the photovoltaic cell is able to be applied on various surfaces.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 25, 2019
    Inventors: Cyprian Emeka Uzoh, Emeka Nchekwube
  • Publication number: 20190189607
    Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 20, 2019
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
  • Publication number: 20190189588
    Abstract: Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Inventor: Cyprian Emeka UZOH
  • Patent number: 10325880
    Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: June 18, 2019
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Sangil Lee, Liang Wang, Guilian Gao
  • Publication number: 20190157199
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Cyprian Emeka UZOH, Charles G. WOYCHIK, Arkalgud R. SITARAM, Hong Shen, Zhuowen SUN, Liang WANG, Guilian GAO
  • Patent number: 10297582
    Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
  • Publication number: 20190148344
    Abstract: Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 16, 2019
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 10290613
    Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Publication number: 20190139878
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Application
    Filed: October 10, 2018
    Publication date: May 9, 2019
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman