Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Abstract: The disclosed technology relates to methods for forming and/or validating bonding surfaces of integrated device dies mounted on a dicing tape, and dicing tapes used thereof. In some embodiments, such a method for forming and validating a microelectronic assembly may include mounting a substrate to a dicing tape; singulating the substrate while the substrate is mounted to the dicing tape to form a plurality of dies; and validating a bonding surface of at least one die of the plurality of dies while the at least one die is mounted to the dicing tape. In some embodiments, such a dicing tape may include an anti-static adhesive layer arranged on an anti-static base film.

Abstract: A method for forming a bonded structure is disclosed. The method can include providing a first element having a first non-conductive region and a first conductive feature, providing a second element having a second non-conductive region and a second conductive feature, bonding the first non-conductive region to the second non-conductive region, and imparting mechanical stress to at least one of the first conductive feature and the second conductive feature. When bonding the first non-conductive region to the second non-conductive region, the first conductive feature and the second conductive feature are spaced apart by a gap. Imparting mechanical stress to the at least one of the first conductive feature and the second conductive feature reduces the gap between the first and second conductive features. The method can include annealing the first and second elements while imparting the mechanical stress to the at least one of the first conductive feature and the second conductive feature.

Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Abstract: An element, a bonded structure including the element, and a method forming the element and the bonded structure are disclosed. The element can include a non-conductive region having a cavity. The element can include a conductive feature formed in the cavity. The conductive feature includes a center portion and an edge portion having first and second coefficients of thermal expansion respectively. The center and edge portions are recessed relative to a contact surface of the non-conductive region by a first depth and a second depth respectively. The first coefficient of thermal expansion can be at least 5% greater than the second coefficient of thermal expansion. The bonded structure can include the element and a second element having a second non-conductive region and a second conductive feature. A conductive interface between the first and second conductive features has a center region and an edge region.

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: An element and a bonded structure including the element are disclosed. The element can include a non-conductive region having a cavity extending at least partially through a thickness of the non-conductive region from the contact surface, and a contact feature formed in the cavity. The non-conductive region is configured to directly bond to a non-conductive region of a second element. The contact pad of the element is configured to directly bond to a contact pad of the second element. The contact pad can include a first conductive material and a second conductive material. The first conductive material can have a unit cell size greater than a unit cell size of the second conductive material. The first conductive material can be a metal alloying material. The first conductive material can be a metal silicide and the second conductive material can be a metal.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.

Abstract: Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

Abstract: Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Abstract: Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.