Patents by Inventor Cyprian Emeka Uzoh

Cyprian Emeka Uzoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132020
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: December 13, 2023
    Date of Patent: October 29, 2024
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • Patent number: 12125784
    Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: October 22, 2024
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
  • Patent number: 12113056
    Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: October 8, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
  • Publication number: 20240334733
    Abstract: A tandem OLED device is formed by patterning a first side of a substrate to form a first OLED opening, forming a first material layer stack in the first OLED opening, the first material layer stack comprising a first charge generation layer (CGL) and a second CGL disposed on the first CGL. After forming the first CGL and the second CGL, a second side of the substrate, opposite the first side, is patterned to form a second OLED opening in registration with the first OLED opening. A second material layer stack is formed in the second OLED opening.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Oliver Zhao, Cyprian Emeka Uzoh, Thomas Workman, Guilian Gao
  • Publication number: 20240332231
    Abstract: Direct bond interconnect in topographic packages and methods of making. The topographic packages include a first die hybrid bonded to a substrate, the first die located in a first device level. A second die located in a second device level above the first device, the second die hybrid bonded to the first die. The topographic packages also include a third die located in a third device level above the second die, the third die hybrid bonded to a top surface of the second device level.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventor: Cyprian Emeka Uzoh
  • Publication number: 20240332267
    Abstract: In some embodiments, a structure comprises an active element having a frontside and a backside opposite the frontside, the active element having active circuitry nearer the frontside than the backside and a power redistribution element having a frontside hybrid bonded to the backside of the active element, the power redistribution element comprising a first plurality of contact pads on the frontside of the power redistribution element and a second plurality of contact pads on a backside of the power redistribution element opposite the frontside of the power redistribution element, a pitch of the first plurality of contact pads is smaller than a pitch of the second plurality of contact pads, the power redistribution element configured to supply at least one of power and ground to the active element.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 3, 2024
    Inventors: Belgacem HABA, Cyprian Emeka UZOH, Rajesh KATKAR
  • Publication number: 20240332248
    Abstract: Direct bond interconnect in topographic packages and methods of making. The topographic packages include a first die hybrid bonded to a substrate, the first die located in a first device level. A second die located in a second device level above the first device, the second die hybrid bonded to the first die. The topographic packages also include a third die located in a third device level above the second die, the third die hybrid bonded to a top surface of the second device level.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventor: Cyprian Emeka Uzoh
  • Publication number: 20240332128
    Abstract: Embodiments herein provide for device packages comprising an integrated cooling assembly and methods of cooling packaged devices. The integrated cooling assembly comprising a semiconductor device, a manifold attached to the semiconductor device, and a sonic transducer attached to the manifold. The manifold comprises a top portion and a waveguide extending downwardly from the top portion. The sonic transducer is attached to the top portion. The top portion, the waveguide, and a backside of the semiconductor device collectively define a coolant chamber volume therebetween.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Rajesh Katkar
  • Publication number: 20240332227
    Abstract: A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Cyprian Emeka Uzoh, Oliver Zhao
  • Publication number: 20240332129
    Abstract: The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 12100676
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 24, 2024
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • Publication number: 20240312953
    Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Inventors: Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, JR., Cyprian Emeka Uzoh
  • Publication number: 20240312954
    Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventor: Cyprian Emeka Uzoh
  • Publication number: 20240312951
    Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 19, 2024
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Gaius Gillman Fountain, JR., Belgacem Haba, Rajesh Katkar
  • Publication number: 20240304593
    Abstract: Disclosed herein are processes and methods for direct bonding. In some embodiments, the process includes providing an element having a dielectric bonding surface and one or more conductive features exposed at the dielectric bonding surface, where the dielectric bonding surface has a planarity suitable for direct bonding. The process also includes, after providing the element, exposing the dielectric bonding surface to the products of a water vapor plasma prior to direct bonding the element.
    Type: Application
    Filed: March 6, 2023
    Publication date: September 12, 2024
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 12087629
    Abstract: Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon are provided. Example structures and processes fabricate conductive vertical pillars for an integrated circuit assembly in a volume of dielectric material instead of in silicon. For example, a block of a silicon substrate may be removed and replaced with dielectric material, and then a plurality of the conductive pillars can be fabricated through the dielectric block. The through-dielectric-vias are shielded from devices and from each other by an intervening thickness of the dielectric sufficient to reduce noise, signal coupling, and frequency losses.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 10, 2024
    Assignee: Adeia Semiconductor Technologies LLC
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 12080672
    Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 3, 2024
    Assignee: ADEIA Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Laura Wills Mirkarimi, Javier A. DeLaCruz, Rajesh Katkar, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Patent number: 12068278
    Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: August 20, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr.
  • Patent number: 12051621
    Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: July 30, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Publication number: 20240249985
    Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.
    Type: Application
    Filed: April 5, 2024
    Publication date: July 25, 2024
    Inventors: Rajesh Katkar, Laura Wills Mirkarimi, Bongsub Lee, Gaius Gillman Fountain, JR., Cyprian Emeka Uzoh