Abstract: A bonded structure comprising a first semiconductor element, a second semiconductor element spaced apart from the first semiconductor element by a gap, and an interconnect assembly comprising an insulating substrate with conductive traces, the insulating substrate including a first section directly bonded to the first semiconductor element, a second section directly bonded to the second semiconductor element, and a flexible section disposed between the first and second sections, the flexible section at least partially bridging the gap.

Abstract: Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

Abstract: Structures and methods for direct bonding are disclosed. A bonded structure can include a first element and a second element. The first element can include a first non-conductive structure that has a non-conductive bonding surface, a cavity that extends at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature that has a first conductive material and a second conductive material over the first conductive material disposed in the cavity. A maximum grain size, in a linear lateral dimension, of the second conductive material can be smaller than 20% of the linear lateral dimension of the conductive feature. There can be less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material.

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.

Abstract: Disclosed is a semiconductor element including a semiconductor portion, a nonconductive layer on the semiconductor portion, an upper conductive layer formed of a first material and at least partially embedded in the nonconductive layer, a lower conductive layer below and electrically connected to the upper conductive layer, and a barrier layer disposed between the upper conductive layer and the lower conductive layer. The barrier layer is formed of a second material different from the first material, and the second material has an electrical resistivity less than 50×10?8 m? at 20° C. and a melting point greater than 1200° C.

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes providing a first element having a first bonding surface, providing a second element having a second bonding surface, slightly etching the first bonding surface, treating the first bonding surface with a terminating liquid treatment to terminate the first bonding surface with a terminating species, and directly bonding the first bonding surface to the second bonding surface without the use of an intervening adhesive and without exposing the first bonding surface to plasma.

Abstract: An element that is configured to bond to another element to define a bonded structure is disclosed. The element can include a dielectric bonding layer having a cavity that extends at least partially through a thickness of the dielectric bonding layer from a surface of the dielectric bonding layer. The element can also include a conductive feature that is at least partially disposed in the cavity. The conductive feature has a contact surface. The element can include a diffusion barrier layer between the conductive feature and a portion of the dielectric bonding layer. The barrier layer includes a barrier metal. The barrier metal of the diffusion barrier layer has an oxidation propensity that is greater than an oxidation propensity of the conductive feature.

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

Abstract: Bonded structures having conductive features and isolation features are disclosed. In one example, a bonded structure can include a first element including a first insulating layer and at least two first conductive features disposed in the first insulating layer. The bonded structure can also include a second element including a second insulating layer and at least two second conductive features disposed in the second insulating substrate. The first element can be directly bonded to the second element with the at least two first conductive features aligned with the at least two second conductive features. The bonded structure can also include an isolation feature in the second insulating layer and between the at least two second conductive features. The isolation feature can have a dielectric constant lower than a dielectric constant of the second insulating layer.

Abstract: Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.

Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.