Abstract: Circuit board inspection by receiving a near infrared (NIR) image of at least a portion of a circuit board, analyzing the NIR image using a machine learning model, and detecting anomalous circuit board portions according to the analysis.

Abstract: Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.

Abstract: Circuit board inspection by receiving a near infrared (NIR) image of at least a portion of a circuit board, analyzing the NIR image using a machine learning model, and detecting anomalous circuit board portions according to the analysis.

Abstract: Embodiments of the invention include a method of singulating IC chips from a wafer. The method can include receiving the wafer having a substrate formed under active layers. The wafer includes a chip that includes a first portion of the active layers and a first portion of the substrate. A separation trench is formed by using an etch operation to remove a first segment of the active layers and a first segment of the substrate that are beneath a first separation channel of the wafer. The separation trench separates the first portion of the active layers from a remaining portion of the active layers; and separates the first portion of the substrate from a remaining portion of the substrate. The first IC chip is seperated from the wafer by removing a first section of the remaining portion of the substrate that is underneath the first portion of the substrate.

Abstract: A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Abstract: A silicon chip carrier includes at least two of a photosensitive P-I-N diode, a non-photosensitive P-I-N diode, a photosensitive P-(metal)-N diode, a non-photosensitive P-(metal)-N diode, and a Schottky diode all integrally formed in the same layers of the chip carrier. In some embodiments, diodes formed in the chip carrier provide photovoltaic power and power regulation to a circuit mounted on the chip carrier.

Abstract: A silicon chip carrier includes at least two of a photosensitive P-I-N diode, a non-photosensitive P-I-N diode, a photosensitive P-(metal)-N diode, a non-photosensitive P-(metal)-N diode, and a Schottky diode all integrally formed in the same layers of the chip carrier. In some embodiments, diodes formed in the chip carrier provide photovoltaic power and power regulation to a circuit mounted on the chip carrier.

Abstract: A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A reactive material erasure element including a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.

Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.

Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.