Patents by Inventor Cyril Cabral

Cyril Cabral has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727121
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 28, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Robert L. Bruce, Cyril Cabral, Jr., Gregory M. Fritz, Eric A. Joseph, Michael F. Lofaro, Hiroyuki Miyazoe, Kenneth P. Rodbell, Ghavam Shahidi
  • Patent number: 10535713
    Abstract: A reactive material erasure element including a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 10446421
    Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cyril Cabral, Jr., Lawrence A. Clevenger, John M. Cohn, Jeffrey P. Gambino, William J. Murphy, Anthony J. Telensky
  • Patent number: 10388615
    Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
  • Publication number: 20190214351
    Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Cyril Cabral, JR., Kenneth P. Rodbell
  • Patent number: 10290594
    Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 10262955
    Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
  • Publication number: 20190096757
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Application
    Filed: November 27, 2018
    Publication date: March 28, 2019
    Inventors: Robert L. Bruce, Cyril Cabral, JR., Gregory M. Fritz, Eric A. Joseph, Michael F. Lofaro, Hiroyuki Miyazoe, Kenneth P. Rodbell, Ghavam Shahidi
  • Patent number: 10214809
    Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Kenneth P. Rodbell
  • Publication number: 20190023963
    Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.
    Type: Application
    Filed: March 20, 2018
    Publication date: January 24, 2019
    Inventors: Cyril Cabral, JR., Gregory M. Fritz, Kenneth P. Rodbell
  • Patent number: 10170361
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert L Bruce, Cyril Cabral, Jr., Gregory M Fritz, Eric A Joseph, Michael F Lofaro, Hiroyuki Miyazoe, Kenneth P Rodbell, Ghavam G Shahidi
  • Publication number: 20180231957
    Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Cyril CABRAL, JR., Lawrence A. CLEVENGER, John M. COHN, Jeffrey P. GAMBINO, William J. MURPHY, Anthony J. TELENSKY
  • Patent number: 10043765
    Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 9991214
    Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
  • Patent number: 9970102
    Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Kenneth P. Rodbell
  • Patent number: 9971341
    Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cyril Cabral, Jr., Lawrence A. Clevenger, John M. Cohn, Jeffrey P. Gambino, William J. Murphy, Anthony J. Telensky
  • Patent number: 9941004
    Abstract: An arming switch structure and method of operation. The arming switch is integrated with a reactive material erasure device and phase change memory cell array and is coupled to a tamper detection device configured to trigger a signal for conduction to the reactive material erasure device that generates heat and induces a phase change in the phase change memory cell array. Prior to packaging, the memory chip is “armed” in a high-resistance state to prevent conduction of any signal to the reactive material erasure device. After the memory chip is packaged, the Reactive Material can be “disarmed” at a chosen time or condition by applying a bias to the arming switch activation layer, thereby heating and crystallizing the arming switch material, placing it in a low resistance state. In the disarmed state, the arming switch may conduct the trigger signal from tamper detection device to the reactive material erasure device.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Cyril Cabral, Jr., Kenneth P. Rodbell
  • Publication number: 20180096954
    Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.
    Type: Application
    Filed: July 28, 2016
    Publication date: April 5, 2018
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Publication number: 20180061782
    Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 1, 2018
    Inventors: Cyril Cabral, JR., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
  • Publication number: 20180047679
    Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 15, 2018
    Inventors: Cyril Cabral, JR., Kenneth P. Rodbell