Patents by Inventor Cyril Cabral
Cyril Cabral has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140070418Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: International Business Machines CorporationInventors: Cyril Cabral, JR., Geraud J.M. Dubois, Daniel C. Edelstein, Takeshi Nogami, Daniel P. Sanders
-
Patent number: 8658461Abstract: A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.Type: GrantFiled: August 3, 2012Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Josephine B. Chang, Alfred Grill, Michael A. Guillorn, Christian Lavoie, Eugene J. O'Sullivan
-
Patent number: 8648465Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: GrantFiled: September 28, 2011Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Geraud Jean-Michel Dubois, Daniel C. Edelstein, Takeshi Nogami, Daniel P. Sanders
-
Patent number: 8633117Abstract: In one embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines. In another embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, wherein the layer of conductive metal is an intermediate layer in the multi-layer structure, etching the multi-layer structure to expose the conductive metal, sputter etching conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines, forming a liner that surrounds the conductive lines, subsequent to the sputter etching, and depositing a dielectric layer on the multi-layer structure.Type: GrantFiled: November 7, 2012Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Cyril Cabral, Benjamin L. Fletcher, Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
-
Publication number: 20130285245Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.Type: ApplicationFiled: March 25, 2013Publication date: October 31, 2013Inventors: Cyril Cabral, Jr., Jeffrey P. Gambino, Qiang Huang, Takeshi Nogami, Kenneth P. Rodbell
-
Publication number: 20130234260Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.Type: ApplicationFiled: April 26, 2013Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Cyril Cabral, Jr., Sebastian U. Engelmann, Benjamin Fletcher, Eric A. Joseph, Satyanarayana V. Nitta
-
Patent number: 8492899Abstract: The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.Type: GrantFiled: October 14, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., John M. Cotte, Kathryn C. Fisher, Laura L. Kosbar, Christian Lavoie, Zhu Liu, Xiaoyan Shao
-
Patent number: 8492897Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.Type: GrantFiled: September 14, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Jeffrey P. Gambino, Qiang Huang, Takeshi Nogami, Kenneth P. Rodbell
-
Patent number: 8431486Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.Type: GrantFiled: August 10, 2010Date of Patent: April 30, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Sebastian U. Engelmann, Benjamin Fletcher, Eric A. Joseph, Satyanarayana V. Nitta
-
Patent number: 8426236Abstract: A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer.Type: GrantFiled: May 7, 2010Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Harold J. Hovel, Xiaoyan Shao
-
Publication number: 20130075908Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., Geraud Jean-Michel Dubois, Daniel C. Edelstein, Takeshi Nogami, Daniel P. Sanders
-
Publication number: 20130062769Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Applicant: International Business Machines CorporationInventors: Cyril Cabral, JR., Takeshi Nogami, Jeffrey P. Gambino, Qiang Huang, Kenneth P. Rodbell
-
Publication number: 20130040454Abstract: A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., Gregory M. Fritz, Christian Lavoie, Conal E. Murray, Kenneth P. Rodbell
-
Patent number: 8362600Abstract: A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.Type: GrantFiled: January 19, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael S. Gordon, David F. Heidel, Conal Eugene Murray, Kenneth Parker Rodbell, Henry Hong Ki Tang
-
Publication number: 20130001784Abstract: A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Cyril Cabral, JR., John M. Cotte, Kathryn C. Fisher, Laura L. Kosbar, Christian Lavoie, Zhu Liu, Kenneth P. Rodbell, Xiaoyan Shao
-
Publication number: 20120326314Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Brown, John Bruley, Cyril Cabral, JR., Sandro Callegari, Martin M. Frank, Michael A. Guillorn, Marinus Hopstaken, Vijay Narayanan, Keith Kwong Hon Wong
-
Publication number: 20120302005Abstract: A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.Type: ApplicationFiled: August 3, 2012Publication date: November 29, 2012Applicant: International Business Machines CorporationInventors: Cyril Cabral, JR., Josephine B. Chang, Alfred Grill, Michael A. Guillorn, Christian Lavoie, Eugene J. O'Sullivan
-
Publication number: 20120267768Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Applicant: International Business Machines CorporationInventors: Paul Stephen Andry, Cyril Cabral, JR., Kenneth P. Rodbell, Robert L. Wisnieff
-
Patent number: 8293643Abstract: A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.Type: GrantFiled: June 21, 2010Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., John M. Cotte, Kathryn C. Fisher, Laura L. Kosbar, Christian Lavoie, Zhu Liu, Kenneth P. Rodbell, Xiaoyan Shao
-
Publication number: 20120261788Abstract: Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.Type: ApplicationFiled: April 15, 2011Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qinghuang Lin, Benjamin L. Fletcher, Cyril Cabral, JR.