Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.

Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.

Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.

Abstract: An arming switch structure and method of operation. The arming switch is integrated with a reactive material erasure device and phase change memory cell array and is coupled to a tamper detection device configured to trigger a signal for conduction to the reactive material erasure device that generates heat and induces a phase change in the phase change memory cell array. Prior to packaging, the memory chip is “armed” in a high-resistance state to prevent conduction of any signal to the reactive material erasure device. After the memory chip is packaged, the Reactive Material can be “disarmed” at a chosen time or condition by applying a bias to the arming switch activation layer, thereby heating and crystallizing the arming switch material, placing it in a low resistance state. In the disarmed state, the arming switch may conduct the trigger signal from tamper detection device to the reactive material erasure device.

Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.

Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.

Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Abstract: An arming switch structure and method of operation. The arming switch is integrated with a reactive material erasure device and phase change memory cell array and is coupled to a tamper detection device configured to trigger a signal for conduction to the reactive material erasure device that generates heat and induces a phase change in the phase change memory cell array. Prior to packaging, the memory chip is “armed” in a high-resistance state to prevent conduction of any signal to the reactive material erasure device. After the memory chip is packaged, the Reactive Material can be “disarmed” at a chosen time or condition by applying a bias to the arming switch activation layer, thereby heating and crystallizing the arming switch material, placing it in a low resistance state. In the disarmed state, the arming switch may conduct the trigger signal from tamper detection device to the reactive material erasure device.

Abstract: A reactive material stack with tunable ignition temperatures is provided by inserting a barrier layer between layers of reactive materials. The barrier layer prevents the interdiffusion of the reactive materials, thus a reaction between reactive materials only occurs at an elevated ignition temperature when a certain energy threshold is reached.

Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.

Abstract: A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Abstract: Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material, Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.