Patents by Inventor Cyril Guyot
Cyril Guyot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12665886Abstract: A client device encodes at least two datasets using one or more encoding functions to generate encoded data portions that are encrypted using a first key according to an approximate Fully Homomorphic Encryption (FHE) scheme to generate encrypted data portions that are sent to a plurality of servers. Encrypted results are received from at least a subset of servers of the plurality of servers. Each encrypted result is calculated by a respective server using at least two encrypted data portions received by the server. The encrypted results are decrypted using a secret key according to the approximate FHE scheme to derive decrypted encoded results that are decoded using an approximate decoding function. In one aspect, an encrypted result is calculated by each server by evaluating a multivariate function using the at least two encrypted data portions received by the server.Type: GrantFiled: August 8, 2023Date of Patent: June 23, 2026Assignee: Western Digital Technologies, Inc.Inventors: Dongwoo Kim, Mahdi Soleymani, Robert Mateescu, Cyril Guyot
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Publication number: 20260093777Abstract: Technology for NAND in-memory compute. NAND memory cells are organized into basic compute engines (CE). A basic CE contains a group of NAND memory cells in the same plane in the memory system. A basic CE may be associated with a set of bit lines in the plane. The memory system may map vectors of leaf nodes of one or more trees to basic CEs and program the vectors of the leaf nodes into basic compute engines in accordance with the mapping. The memory system perform an in-memory vector-vector multiplication in parallel between an input vector and each of the vectors of one or more of the leaf nodes in one or more of the basic compute engines.Type: ApplicationFiled: October 2, 2024Publication date: April 2, 2026Applicant: Sandisk Technologies, Inc.Inventors: Chao Sun, Muqing Liu, Cyril Guyot
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Publication number: 20250390733Abstract: A computing system is provided that includes at least one processing unit, at least one high bandwidth memory (HBM) unit, and at least one high bandwidth flash (HBF) unit. The HBM and HBF units are all in electrical communication with the at least one processing unit. The computing system also includes control circuitry that is configured to train a large language model according to a low-rank adaptation (LoRA) technique. The control circuitry is configured to store a full-weight matrix in the at least one HBF unit and to store at least one low-rank matrix in the at least one HBM unit.Type: ApplicationFiled: June 20, 2024Publication date: December 25, 2025Inventors: Cyril Guyot, Robert Eugeniu Mateescu, Minghai Qin
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Publication number: 20250370976Abstract: To accelerate search speeds for approximate nearest neighbor searches of vector databases, compute-in-memory techniques using NAND memory structures are introduced. For each element of the database, a kernel of its M nearest neighbors is determined. For each vector of the database, both the vector and its kernel are programmed in the arrays of a NAND memory based accelerator card, so that the vectors will be written into the memory arrays both as themselves and also in kernels of vectors for which they are a nearest neighbor. Metadata, associating the locations of the kernel members with the correspond vector is also stored in the memory system. After determining the input's nearest neighbor at one level of search, the metadata is then used to locate that nearest neighbor's nearest neighbors and their distances to the input vector are then computed in parallel in a compute-in-memory vector-vector dot product multiplication.Type: ApplicationFiled: May 30, 2024Publication date: December 4, 2025Applicant: Sandisk Technologies, Inc.Inventors: Chao Sun, Muqing Liu, Cyril Guyot
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Patent number: 12450119Abstract: A storage device minimizes redundancy for stuck bit codes when writing a message to a memory device. A controller generates a set of masks that are codewords and that include values that correspond to stuck bit values. The set of masks may include full length codewords or shortened codewords. When the controller receives a message including a predefined number of label bits and determines that a location in the memory device where the message is be stored includes two stuck bits, the controller encodes the message to produce a first message codeword. The controller then locates a mask from the set of masks, wherein when the mask is added to the first message codeword, any two stuck message bits are masked. The controller computes a final message codeword using the first message codeword and the mask and stores the final message codeword on the memory device.Type: GrantFiled: December 8, 2023Date of Patent: October 21, 2025Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ivana Djurdjevic, Cyril Guyot, Robert Mateescu
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Patent number: 12450477Abstract: Certain aspects of the present disclosure provide techniques for performing machine learning, including: processing a training data instance with a task model to generate an encoding and a task model output; processing a discriminator input based on the encoding using a discriminator model to generate an estimated mutual information between the encoding and the one or more input variables of the training data instance; updating parameters of the discriminator model using a first iterative optimization algorithm to maximize a discriminator objective function based on the estimated mutual information; and updating parameters of the task model using a second iterative optimization algorithm to minimize a task objective function based on a sum of the estimated mutual information between the task model output and the one or more input variables of the training data instance and a conditional entropy between the target variable and an encoding generated by the task model.Type: GrantFiled: August 23, 2021Date of Patent: October 21, 2025Assignee: Western Digital Technologies, Inc.Inventors: Qing Li, Yongjune Kim, Cyril Guyot
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Publication number: 20250307344Abstract: To reduce programming noise for matrix values stored in a memory array for use in an in-array vector-matrix multiplication, such as for a neural network, the matrix is partitioned into a linear combination of matrices that will preserve the output after the combination, with the small value component matrices being normalize to the lager, full range of values before being programmed into the memory arrays. After multiplying each matrix of the combination with the vector by applying a set of bias values, the outputs are rescaled to undo the normalization before adding the individual outputs back together for the final output. This re-scaling causes the effective noise of small weights to be reduced, providing large noise tolerance for these small weight values.Type: ApplicationFiled: March 27, 2024Publication date: October 2, 2025Applicant: SanDisk Technologies LLCInventors: Minghai Qin, Martin Lueker-Boden, Cyril Guyot, Richard New
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Publication number: 20250307601Abstract: To reduce noise for compute in memory vector-matrix multiplications using non-volatile memory, such in large language models or other neural networks, the matrix of values is independently programmed in multiple arrays. The input vector is then independently applied to the multiple arrays to generate a corresponding set of multiple results. The independent results can then be combined by ensemble algorithms, as an averaging, to generate the output. The combined output can then be used as input to a subsequent layer of weights, which can again be independently written in to multiple arrays.Type: ApplicationFiled: March 27, 2024Publication date: October 2, 2025Inventors: Minghai Qin, Cyril Guyot, Richard New
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Patent number: 12430650Abstract: Systems, methods, and devices described herein can configure a cryptocurrency wallet or other blockchain-based account to be self-aware and alert the owner of the wallet to one or more potentially fraudulent situations occurring with at least one account they own. The wallet may be a hardware-based cryptocurrency wallet or may be a blockchain-based account operating by an external financial institution that allows for the management of cryptocurrency assets. The self-aware wallet can be configured to track all relevant previously known and/or approved transactions associated with a user's private cryptocurrency key. A subsequent scan on one or more blockchains is performed to detect new transactions associated with the user's private key. If a newly detected blockchain transaction is not in the list of previously known or approved user transactions, a potential compromise may be occurring. Once detected, the wallet can generate a notification to the user alerting them to the issue.Type: GrantFiled: January 20, 2023Date of Patent: September 30, 2025Assignee: Western Digital Technologies, Inc.Inventors: Shashank Agrawal, Cyril Guyot, Evan Drake
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Publication number: 20250238202Abstract: Multiply and accumulate (MAC) operations typically involve extremely large amounts of data and large numbers of operations. As such, they are extremely computationally intensive, involving large numbers of data transfers and consuming large amounts of time and power. To address these problems, the following presents methods of realizing a MAC engine in a 3D NAND flash die. The engine takes as input two vectors and outputs their dot product. The dot product of two vectors is the building block of matrix multiplication. The 3D NAND MAC engine presented here can be used to implement modern machine learning algorithms, in particular Neural Networks. The two vector operands are not programed into the NAND memory cells, therefore the endurance of the device is not compromised.Type: ApplicationFiled: January 19, 2024Publication date: July 24, 2025Applicant: Western Digital Technologies, Inc.Inventors: Robert Mateescu, Cyril Guyot, Richard New
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Patent number: 12362029Abstract: A storage device processes storage-free stuck bits information when writing and reading stored on the memory device. A controller encodes the data with cyclic error-correcting codes to generate a codeword and determines that a location in the memory device where codeword is be stored includes a stuck bit. Rather than storing the stuck bits information, when storing the codeword, the controller generates an encoding mask, adds the encoding mask to the codeword to generate encoded data, and stores the encoded data on the memory device. When reading the encoded data, the controller generates a list of decoding masks including the encoding mask, goes through the lists and adds a decoding mask to the encoded data. The controller decodes the encoded data with the encoding mask from the list and returns the data.Type: GrantFiled: November 13, 2023Date of Patent: July 15, 2025Assignee: Western Digital Technologies, Inc.Inventors: Robert Mateescu, Cyril Guyot, Ivana Djurdjevic
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Publication number: 20250190302Abstract: A storage device minimizes redundancy for stuck bit codes when writing a message to a memory device. A controller generates a set of masks that are codewords and that include values that correspond to stuck bit values. The set of masks may include full length codewords or shortened codewords. When the controller receives a message including a predefined number of label bits and determines that a location in the memory device where the message is be stored includes two stuck bits, the controller encodes the message to produce a first message codeword. The controller then locates a mask from the set of masks, wherein when the mask is added to the first message codeword, any two stuck message bits are masked. The controller computes a final message codeword using the first message codeword and the mask and stores the final message codeword on the memory device.Type: ApplicationFiled: December 8, 2023Publication date: June 12, 2025Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: IVANA DJURDJEVIC, CYRIL GUYOT, ROBERT MATEESCU
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Publication number: 20250157562Abstract: A storage device processes storage-free stuck bits information when writing and reading stored on the memory device. A controller encodes the data with cyclic error-correcting codes to generate a codeword and determines that a location in the memory device where codeword is be stored includes a stuck bit. Rather than storing the stuck bits information, when storing the codeword, the controller generates an encoding mask, adds the encoding mask to the codeword to generate encoded data, and stores the encoded data on the memory device. When reading the encoded data, the controller generates a list of decoding masks including the encoding mask, goes through the lists and adds a decoding mask to the encoded data. The controller decodes the encoded data with the encoding mask from the list and returns the data.Type: ApplicationFiled: November 13, 2023Publication date: May 15, 2025Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: ROBERT MATEESCU, CYRIL GUYOT, IVANA DJURDJEVIC
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Patent number: 12261961Abstract: Blockchain systems operate over a network of computing devices. Proof of space blockchain consensus systems utilize data stored in storage devices across the computing devices within the network. These storage devices are utilized to generate and store proof of space consensus data. This data is then accessed at a later time to respond to challenges issued across the blockchain network. In order to limit successful submissions of these challenge responses, one or more filters are utilized. These filters result in only a fraction of the stored data on a storage device to be useable for solving the blockchain challenge. Attackers may attempt to circumvent this filter to increase their odds of submitting an approved solution to the blockchain challenge. In order to address this, additional data structures are stored within the storage device and are registered at the time of creation on the blockchain to make these filters more robust.Type: GrantFiled: December 17, 2021Date of Patent: March 25, 2025Assignee: Western Digital Technologies, Inc.Inventors: Shashank Agrawal, Cyril Guyot
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Patent number: 12182430Abstract: Certain aspects of the present disclosure provide techniques for proving possession of data in a storage device participating in a distributed data storage network. An example storage device includes a storage circuitry and a trusted circuit. The storage circuitry is configured to store a plurality of data blocks. The trusted circuit generally has a private signing key securely stored thereon. The trusted circuit is generally configured to compute a hash over data stored in a plurality of data blocks and to generate an anonymous digital signature for the data stored in the plurality of data blocks based at least in part on the private signing key and the computed hash. The trusted circuit may be interposed on a write path to the storage circuitry such that data written to the storage circuitry is processed through the trusted circuit.Type: GrantFiled: November 29, 2021Date of Patent: December 31, 2024Assignee: Sandisk Technologies, Inc.Inventors: Shashank Agrawal, Cyril Guyot
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Patent number: 12137164Abstract: Techniques for storage-free message authentication for error-correcting-codes are disclosed. A storage controller of a storage device receives a request to encode a message in a format having an error-correcting code schema that generates a parity code. A key generator generates a pseudorandom transposition of the message and the parity code as a first part of a secret key. A pseudorandom character string is determined as a second part of the secret key. The output of the pseudorandom transposition and the pseudorandom character string are combined to generate the encoded message which is returned in response to the request. The secret key associated with the message is stored in non-volatile memory.Type: GrantFiled: August 10, 2023Date of Patent: November 5, 2024Assignee: Sandisk Technologies, Inc.Inventors: Dongwoo Kim, Cyril Guyot
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Patent number: 12052375Abstract: Blockchain systems operate over a network of computing devices. Proof-of-space blockchain consensus systems utilize data (called plots) stored in storage devices across the computing devices within the network. These storage devices are utilized to generate and store proof-of-space consensus data. This data is then accessed at a later time to respond to challenges issued across the blockchain network. The owner of a plot may wish to sell a plot to another miner. If the seller is a bad-faith actor, they may retain copies of the secret key(s) and use them to continue mining the plot along with the buyer. To prevent these attacks, it may be desirable to submit a challenge response block where the proof-of-space is not visible as part of the challenge response. This may be done by replacing the proof-of-space with a proof-of-knowledge.Type: GrantFiled: April 6, 2022Date of Patent: July 30, 2024Assignee: Western Digital Technologies, Inc.Inventors: Shashank Agrawal, Cyril Guyot
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Publication number: 20240171372Abstract: A client device encodes one or more input datasets of real numbers into a plaintext polynomial with integral coefficients that do not include an imaginary component and generates an input ciphertext by encrypting the plaintext polynomial according to a Fully Homomorphic Encryption (FHE) scheme. The input ciphertext includes at least encrypted coefficients of an input polynomial. A server receives the input ciphertext and performs a convolution on the input ciphertext using a kernel by at least in part separately multiplying the input polynomial by one or more kernel polynomials to result in one or more corresponding convolved polynomials. The one or more kernel polynomials include kernel coefficients encoded using kernel values for the kernel. At least a plurality of coefficients is used from each of the one or more convolved polynomials to derive an output ciphertext representing an output of the convolution on the input ciphertext using the kernel.Type: ApplicationFiled: August 8, 2023Publication date: May 23, 2024Inventors: Dongwoo Kim, Cyril Guyot
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Publication number: 20240146700Abstract: A client device encodes at least two datasets using one or more encoding functions to generate encoded data portions that are encrypted using a first key according to an approximate Fully Homomorphic Encryption (FHE) scheme to generate encrypted data portions that are sent to a plurality of servers. Encrypted results are received from at least a subset of servers of the plurality of servers. Each encrypted result is calculated by a respective server using at least two encrypted data portions received by the server. The encrypted results are decrypted using a secret key according to the approximate FHE scheme to derive decrypted encoded results that are decoded using an approximate decoding function. In one aspect, an encrypted result is calculated by each server by evaluating a multivariate function using the at least two encrypted data portions received by the server.Type: ApplicationFiled: August 8, 2023Publication date: May 2, 2024Inventors: Dongwoo Kim, Mahdi Soleymani, Robert Mateescu, Cyril Guyot
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Patent number: 11921644Abstract: Various processes for efficiently and effectively managing huge pages include a process for optimizing memory deduplication of huge pages, optimizing the promotion of one or more base pages to one or more huge pages and optimizing memory compaction of a memory space associated with a huge page.Type: GrantFiled: May 20, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Qing Li, Cyril Guyot