Patents by Inventor Cyril Guyot

Cyril Guyot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9208871
    Abstract: A method and apparatus are provided for implementing enhanced data read for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data read back for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, higher voltage and lower voltage levels are compared, and respective data values are identified responsive to the compared higher voltage and lower voltage levels.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: December 8, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Luiz M. Franca-Neto, Cyril Guyot, Robert Eugeniu Mateescu
  • Patent number: 9153290
    Abstract: A head-assisted magnetic recording-shingled magnetic recording (HAMR-SMR) type storage device is described that includes a control module and one or more magnetic recording layers partitioned into zones. The control module is configured to write initial data beginning at an initial logical address of a zone. The initial logical address of the zone corresponds to an initial physical address of the zone. Responsive to receiving a command from a host associated with the HAMR-SMR type storage device to reset the zone and write subsequent data, the control module is further configured to reset the initial logical address of the zone to a subsequent physical address of the zone, and after resetting the initial logical address, write the subsequent data beginning at the initial logical address of the zone.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: October 6, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Luiz M. Franca-Neto, Cyril Guyot, Adam C. Manzanares, Bruno Marchon, Erhard Schreck
  • Patent number: 9070483
    Abstract: A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: June 30, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Robert Eugeniu Mateescu, Luiz Franca-Neto, Cyril Guyot, Hessam Mahdavifar, Zvonimir Bandic, Qingbo Wang
  • Publication number: 20150177994
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Application
    Filed: February 25, 2015
    Publication date: June 25, 2015
    Inventors: Dejan VUCINIC, Zvonimir Z. BANDIC, Cyril GUYOT, Robert MATEESCU, Qingbo WANG
  • Publication number: 20150154120
    Abstract: Systems, methods, and firmware for operating data storage devices and storage processors are provided herein. In one example, a data storage device is provided. The data storage device includes phase change media on which to write data, and a processing system configured to identify a write process to at least obfuscate an acoustic signature associated with writing the data on the phase change media and write the data to the phase change media in accordance with the write process.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Dejan Vucinic, Luiz Franca-Neto
  • Patent number: 9047311
    Abstract: Approaches for retrieving files from a replicated file system. A component receives, from a requestor, a request for a copy of a data unit. The component identifies a plurality of storage nodes that each stores a complete copy of the data unit. The component sends, to the plurality of storage nodes, an instruction to retrieve a copy of the data unit within a specified period of time. At each storage node receiving an instruction, a determination of whether the copy of the data unit may be retrieved within the specified period of time is made, and if so, the copy of the data unit is provided to the component only if the copy of the data unit was actually retrieved within the specified period. The component provides the first copy of the data unit it receives to the requestor and discards any subsequently received copies of the data unit.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 2, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Bandic, Filip Blagojevic, Cyril Guyot, Timothy Tsai, Qingbo Wang
  • Publication number: 20150143187
    Abstract: A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Robert Eugeniu Mateescu, Dejan Vucinic, Cyril Guyot
  • Patent number: 8996955
    Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: March 31, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Luiz Franca-Neto, Robert Eugeniu Mateescu, Cyril Guyot
  • Publication number: 20150081956
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 19, 2015
    Inventors: Dejan VUCINIC, Zvonimir Z. BANDIC, Qingbo WANG, Cyril Guyot, Robert Mateescu, Frank R. Chu
  • Publication number: 20150081947
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Application
    Filed: August 22, 2014
    Publication date: March 19, 2015
    Inventors: Dejan VUCINIC, Zvonimir Z. BANDIC, Qingbo WANG, Cyril Guyot, Robert Mateescu, Frank R. Chu
  • Publication number: 20150081955
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 19, 2015
    Inventors: Dejan VUCINIC, Cyril GUYOT, Robert MATEESCU
  • Publication number: 20150081933
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Application
    Filed: August 22, 2014
    Publication date: March 19, 2015
    Inventors: Dejan VUCINIC, Cyril GUYOT, Robert MATEESCU, Qingbo WANG, Zvonimir Z. BANDIC, Frank R. CHU
  • Publication number: 20150082084
    Abstract: Systems, methods, and firmware for recovery of data from storage devices are provided herein. In one example, a data storage device is provided. The data storage device includes a storage portion and a cache portion which caches data intended for storage in the storage portion. Responsive to a recovery read command identifying requested data, the data storage device retrieves stored data corresponding to the requested data from the storage portion without retrieving cached data corresponding to the requested data from the cache portion that supersedes at least a portion of the stored data. Responsive to a cache block list command, the data storage device transfers a list identifying one or more cached blocks of the cached data. Responsive to a read command that identifies at least one cached block, the data storage device retrieves the at least one cached block.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Zvonimir Bandic
  • Patent number: 8943388
    Abstract: A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 27, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Luiz Franca-Neto, Robert Eugeniu Mateescu, Hessam Mahdavifar, Zvonimir Bandic, Qingbo Wang
  • Patent number: 8941944
    Abstract: A method of radially positioning a heat assisted magnetic recording (HAMR) head writes data to a first band, wherein a radial position of the HAMR head within each data track is defined by a positional bias and a track location. A determination is made regarding whether a threshold has been reached with respect to the first band. If the write threshold has been reached with respect to the first band, then the positional bias associated with the first band is modified to evenly distribute thermal exposure of data tracks in the first band.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 27, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Qing Dai, Xing-Cai Guo, Cyril Guyot, Lidu Huang, Bruno Marchon, Erhard Schreck
  • Patent number: 8909859
    Abstract: A method and a storage system are provided for implementing a sustained large block random write performance mechanism for shingled magnetic recording (SMR) drives in a redundant array of inexpensive disks (RAID). A Solid State Drive (SSD) is provided with the SMR drives in the RAID. The SSD is used in a hot spare mode, which is activated when a large block random-write event is identified for a SMR drive in the RAID. In the hot spare mode, the SSD temporarily receives new incoming writes for the identified SMR drive. Then the identified SMR drive is updated from the SSD to restore the state of the identified SMR drive, and operations continue with normal writing only using the SMR drives in the RAID.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: December 9, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Cyril Guyot, Tomohiro Harayama, Hitoshi Kamei, Takaki Nakamura, Timothy Tsai
  • Patent number: 8892817
    Abstract: Methods are described that allow disk drives, such as shingle-written magnetic recording (SMR) drives, to recover an Indirection Address Table mapping of LBAs to PBAs after an emergency power off (EPO). Indirection Address Table (IAT) snapshots are periodically written inline with user data stores, and in one embodiment Cumulative Delta Lists (CDLs) with incremental address update information are stored between snapshots. In an embodiment of the invention, when an imminent loss of power is detected, the current CDL, covering IAT updates not yet written to disk, is saved to a nonvolatile memory. The IAT snapshots combined with the set of CDLs provide the information needed to recreate the current Indirection Address Table when power is restored after an emergency power loss. In an alternative embodiment the CDL is obviated by including metadata in the sector that encodes the address indirection mapping and the last snapshot ID.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: November 18, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Yuval Cassuto, Jonathan Darrel Coker, Cyril Guyot, Marco Sanvido
  • Patent number: 8887025
    Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: November 11, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Robert Eugeniu Mateescu, Luiz Franca-Neto, Cyril Guyot, Hessam Mahdavifar, Zvonimir Bandic, Qingbo Wang
  • Patent number: 8874875
    Abstract: ICC-NCQ priority and deadline information in conjunction with an estimation of command access time that is specific to SMR drives are used improve command queue optimization. Estimated completion times are determined based on the internal subcommands that the drive has to execute to complete the host read or write command taking into account whether all or part of the data will be or already is stored in write-twice cache, E-region and/or I-region. The command processor selects the next command for execution based on calculated access times with adjusted priority based on the specified deadline for the command. As the deadline approaches, the priority of the command increases. For high priority data writes as specified by a host, an optimized storage plan is selected as appropriate using the “write-twice cache” (WTC) region, E-region or I-region.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 28, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Cyril Guyot
  • Patent number: 8838841
    Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 16, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Timothy K. Tsai