Abstract: The invention discloses a method and an apparatus for reconstructing a parallel-acquired image, comprising: generating reconstruction data by combining uniformly under-sampled data and low-frequency fully-sampled data in MRI K-space according to a hybrid sampling mode; calculating the sensitivity distribution of a coil according to said low-frequency fully-sampled data; and reconstructing an image according to the reconstruction data, the coil's sensitivity distribution and the hybrid sampling mode. The signal to noise ratio of the reconstructed image is effectively improved by using the reconstruction data combined with the low-frequency fully-sampled data in reconstructing the image since the low-frequency fully-sampled data contains more useful information.

Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

Abstract: A receiving device for an MRI (magnetic resonance imaging) system has multiple receiving coils. In the same imaging acceleration direction, a junction region is formed between adjacent receiving coils. An additional receiving coil is arranged on the junction region. The additional receiving coil covers at least partially a line of strong phase variation in sensitivity at the boundary of said junction region. This receiving device alleviates the problem of poor sensitivity to MRI signals in the junction region in the imaging acceleration direction, so as to improve the imaging quality in the junction region, and thus improving the overall imaging quality.

Abstract: In a method and apparatus for correcting distortion during magnetic resonance imaging k space data in a number of readout encoding directions, wherein the sampling points on the phase encoding lines are concentrated in low frequency regions and their number is less than that of full sampling points. A view angle tilting compensation gradient is superimposed on the axis of a layer selection gradient. The k space data acquired from the number of directions are then combined. Due to the fact that the superimposition of the view angle tilting compensation gradient on the axis of the slice selection gradient can effectively correct geometric distortions, and at the same time the resolution in phase encoding lines is relatively high, low resolution contents are provided only in readout encoding directions, so the degree of blurring in the final image is substantially reduced. Furthermore, by acquiring the k space data in a number of readout directions the sensitivity to motion artifacts can effectively be reduced.

Abstract: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.

Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor.

Abstract: Different circuit-based implementations of stochastic anti-windup PI controllers are provided for a motor drive controller system. The designs can be implemented in a Field Programmable Gate Arrays (FPGA) device. The anti-windup PI controllers are implemented stochastically so as to enhance the computational capability of FPGA.

Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Abstract: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Abstract: A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

Abstract: A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Abstract: The invention discloses a method and an apparatus for reconstructing a parallel-acquired image, comprising: generating reconstruction data by combining uniformly under-sampled data and low-frequency fully-sampled data in MRI K-space according to a hybrid sampling mode; calculating the sensitivity distribution of a coil according to said low-frequency fully-sampled data; and reconstructing an image according to the reconstruction data, the coil's sensitivity distribution and the hybrid sampling mode. The signal to noise ratio of the reconstructed image is effectively improved by using the reconstruction data combined with the low-frequency fully-sampled data in reconstructing the image since the low-frequency fully-sampled data contains more useful information.

Abstract: The invention discloses a method for calculating the signal-to-noise ratio (SNR) in parallel acquisition image reconstruction, comprising: determining a reconstruction expression for a linear operation of the image reconstruction; determining a weighted coefficient according to the reconstruction expression; calculating the SNR according to the weighted coefficient and the raw data. The SNR not only is relevant to the geometric shape and position of the coils, but also is influenced by the reconstruction method and the sampling mode. The SNR is calculated based on contribution of the raw data at positions in the reading direction from all the phase-coding lines in all acquisition channels. It reflects more precisely the loss of the SNR in the parallel acquisition image reconstruction, especially the changes in the SNR caused by the number of the reference lines combined during the reconstruction.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.

Abstract: A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.