Abstract: A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially to fill the source/drain recesses and thereby create source/drain structures. Exposed dielectric on the substrate upper surface may be removed using an HF dip prior to forming the source/drain recesses. Preferably, the NH4OH solution has an NH4OH concentration of less than approximately 0.5% and is maintained a temperature in the range of approximately 20 to 35° C. The silicon-bearing epitaxial compound may be silicon germanium for PMOS transistor or silicon carbide for NMOS transistors. A silicon dry etch process may be performed prior to the NH4OH wet etch to remove a surface portion of the source/drain regions.

Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Abstract: A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer is epitaxially grown in the etch-recessed region.

Abstract: In one embodiment, a top surface of a semiconductor device (18) is amorphized in a tool (1). A metal is deposited over the semiconductor substrate using the same tool. In one embodiment, the same chambers are used. In an embodiment, the tool is a sputtering tool, such as a physical vapor deposition (PVD). The semiconductor substrate may be annealed to form a metal silicide (122) over at least a portion of the semiconductor device that includes silicon.

Abstract: A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.

Abstract: A method of introducing conjugated caps onto molecular fragments is described. A first molecule may be decomposed or cut into molecular fragments. Molecular caps may then be introduced in the form of conjugated caps onto the molecular fragments at the decomposition points to form molecular portions. The interaction energy between the molecular portion and a second molecule can then be calculated. This scheme, termed molecular fractionation with conjugated caps, makes it possible and practical to carry out full quantum mechanical (ab initio) calculation of intermolecular interaction energies involving molecules, such as proteins or other biological molecules.

Abstract: A method for depositing a barrier or coating layer (34) in a semiconductor recessed structure (28) within a substrate (20) using a plasma process (62) that includes alternating depositing steps (64) and resputtering steps (66). The depositing step (64) deposits a barrier layer (34), including a thick bottom region (38) and a sidewall region (40) along the recessed structure (28) surface. The resputtering step (66) reduces the barrier layer (34) thickness in the bottom region (38) and increases the barrier layer (34) thickness in the otherwise thinly covered portions of the substrate sidewall region (40). Control of powers ranges supplied to the sputtering target (14) and the substrate (20) achieve the depositing and resputtering steps. The process applies also to other coating layers than barrier layers (34), providing a uniform sidewall coverage and thin bottom coverage, e.g., for permalloy deposition in MRAM devices and dual gate electrode formation in CMOS devices.

Abstract: A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.

Abstract: A method for reducing the resistance within an opening, such as a via, in a dielectric (230) is described herein. A first barrier layer (250) is formed within the opening and the portion of the first barrier layer (250) at the bottom of the opening is removed, thereby exposing an underlying metal line (210). Deposited within the opening over the first barrier layer (250) and in contact with a conductor (210), a thin second barrier layer (260) forms a barrier between the conductor (210) and subsequently formed conductive material (270 and 280) within the opening. Because the second barrier layer (260) is thin, resistance is minimized between the conductor (210) and the conductive material (270 and 280). Additionally, if the opening is not aligned with the metal line (210), the second barrier layer (260) prevents the conductive material (270 and 280) from degrading an underlying dielectric (220) that may be present underneath the opening.