Patents by Inventor Dae-gyu Park
Dae-gyu Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150236118Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.Type: ApplicationFiled: April 29, 2015Publication date: August 20, 2015Inventors: KEVIN K. CHAN, YOUNG-HEE KIM, ISAAC LAUER, RAMACHANDRAN MURALIDHAR, DAE-GYU PARK, XINHUI WANG, MIN YANG
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Patent number: 9105741Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.Type: GrantFiled: September 13, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Jinghong Li, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Qingyun Yang
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Patent number: 9099585Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.Type: GrantFiled: September 6, 2012Date of Patent: August 4, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Publication number: 20150214364Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Jinghong Li, Dae-Gyu Park
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Publication number: 20150179739Abstract: A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Cheng-Wei Cheng, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Dae-Gyu Park, Devendra K. Sadana
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Patent number: 9059016Abstract: A lateral heterojunction bipolar transistor is formed on a substrate including a top semiconductor layer of a first semiconductor material having a first band gap and of a first conductivity type. A stack of an extrinsic base and a base cap is formed over the top semiconductor layer. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor layer that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap, having a doping of the second conductivity type and being lattice matched to the first semiconductor material is selectively deposited to form an emitter contact region and a collector contact region, respectively.Type: GrantFiled: February 14, 2014Date of Patent: June 16, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Dae-Gyu Park, Ghavam G. Shahidi
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Patent number: 9054192Abstract: A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin.Type: GrantFiled: December 20, 2013Date of Patent: June 9, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Cheng-Wei Cheng, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Dae-Gyu Park, Devendra K. Sadana
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Patent number: 9048261Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.Type: GrantFiled: August 4, 2011Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
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Patent number: 9034748Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.Type: GrantFiled: September 4, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Christopher V. Baiocco, Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Fei Liu, Dae-Gyu Park, Helen Wang, Xinhui Wang, Min Yang
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Patent number: 9023697Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.Type: GrantFiled: August 8, 2013Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Min Yang, Qi Zhang
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Publication number: 20150064897Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Christopher V. Baiocco, Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Fei Liu, Dae-Gyu Park, Helen Wang, Xinhui Wang, Min Yang
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Publication number: 20150041911Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicants: GLOBALFOUNDRIES, INC., International Business Machines CorporationInventors: KEVIN K. CHAN, DAE-GYU PARK, XINHUI WANG, YUN-YU WANG, MIN YANG, QI ZHANG
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Publication number: 20150041858Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.Type: ApplicationFiled: October 24, 2014Publication date: February 12, 2015Inventors: KEVIN K. CHAN, DAE-GYU PARK, XINHUI WANG, YUN-YU WANG, MIN YANG, QI ZHANG
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Publication number: 20140299882Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.Type: ApplicationFiled: April 5, 2013Publication date: October 9, 2014Applicant: International Business Machines CorporationInventors: Kevin K. Chan, Babar A. Khan, Dae-Gyu Park, Xinhui Wang
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Publication number: 20140225199Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: ApplicationFiled: April 17, 2014Publication date: August 14, 2014Applicant: International Business Machines CorporationInventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
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Patent number: 8778448Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.Type: GrantFiled: July 21, 2011Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 8753936Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: GrantFiled: August 12, 2008Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
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Patent number: 8748252Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.Type: GrantFiled: November 26, 2012Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang
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Publication number: 20140148003Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang
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Publication number: 20140070316Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Jinghong Li, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Qingyun Yang