Abstract: The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.

Abstract: The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.

Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

Abstract: A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An aluminum oxide (Al2O3) layer is deposited on top of the semiconductor substrate and then, silicon ions plasma doping is carried out. Thereafter, the Al2O3 layer doped with silicon ions is annealed in the presence of oxygen gas or nitrous oxygen to remove a metallic vacancy in the Al2O3 layer. Subsequently, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.

Abstract: There is disclosed a method of forming a gate electrode in a semiconductor device. The present invention forms a gate insulating film using (TiO2)x(Al2O3)x-1 in which a titanium oxide film (TiO2) having a high dielectric constant and an aluminum oxide film having leakage and interfacial property are mixed. Therefore, the present invention could not only improve the leakage current characteristic of a semiconductor device but also early develop a high-speed device having a high density in the future.

Abstract: A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaOxNy film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO2 or SiON film on the semiconductor substrate, depositing an amorphous TaOxNy film on the SiO2 or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaOxNy film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaOxNy film, and crystallize the amorphous TaOxNy film, and depositing a metal barrier film on the crystallized TaOxNy film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

Abstract: A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a NMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An ultra thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2 at a temperature ranging from approximately 650° C. to approximately 900° C. And then, an Al layer is deposited on top of the semiconductor substrate and annealed in the presence of oxygen gas or nitrous oxygen to convert the Al layer into an Al2O3 layer. Thereafter, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.

Abstract: There is disclosed a method of manufacturing a semiconductor device utilizing a gate dielectric film. The present invention can obtain a (Al2O3)X—(TiO2)1−X gate dielectric film where its the dielectric constant is higher than that of Al2O3 and its leakage current characteristic is improved compared to TiO2, by depositing a Ti1−XAlXN film on a semiconductor substrate and then forming the (Al2O3)X—(TiO2)1−X gate dielectric film by oxidization process. Therefore, the present invention can implement a high-speed high-density logic device and an ultra high integration device of more than 1G DRAM class, which utilize a high dielectric material as the gate dielectric film.