Patents by Inventor Dae Han Kwon

Dae Han Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847194
    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Dae Han Kwon, Kwan Su Shon, Soon Ku Kang, Jung Hyun Shin, Doo Bock Lee, Yo Han Jeong, Eun Ji Choi, Tae Jin Hwang
  • Publication number: 20200293082
    Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Applicant: SK hynix Inc.
    Inventors: Soo Young JANG, Dae Han KWON, Geun Il LEE, Kyu Dong HWANG
  • Patent number: 10766985
    Abstract: The present invention relates to an olefin polymer and a preparation method thereof. The olefin polymer exhibits excellent mechanical strength and high processability, and thus is expected to be utilized as a material for various products. Particularly, the olefin polymer can be stably produced into films by a melt-blowing process and thus is expected to be usefully used as a material for products prepared by a melt-blowing process.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: September 8, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Sol Cho, Sung Hyun Park, Oh Joo Kwon, Ki Soo Lee, Heon Yong Kwon, Dae Sik Hong, Myung Han Lee, Hyun Jee Kwon
  • Patent number: 10742182
    Abstract: A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Sun Ki Cho, Dae Han Kwon
  • Patent number: 10734951
    Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 4, 2020
    Assignees: SK hynix Inc., NORTHEASTERN UNIVERSITY
    Inventors: Hae Kang Jung, Yong Suk Choi, Yong Bin Kim, Gyunam Jeon, Dae-Han Kwon, Joo Hwan Cho
  • Patent number: 10720199
    Abstract: A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Kyu Dong Hwang, Dae Han Kwon
  • Patent number: 10600457
    Abstract: A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Bo Ram Kim, Dae Han Kwon
  • Patent number: 10508164
    Abstract: The low density polyethylene copolymer according to the present invention is characterized in that as LCB (Long Chain Branch) is introduced into LLDPE, the melt strength is remarkably high even without blending with LDPE, and thus it can be advantageously applied to blown film processing and the like.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 17, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Oh Joo Kwon, Sol Cho, Ki Soo Lee, Heon Yong Kwon, Dae Sik Hong, Sung Hyun Park, Myung Han Lee
  • Publication number: 20190356289
    Abstract: A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.
    Type: Application
    Filed: December 4, 2018
    Publication date: November 21, 2019
    Applicant: SK hynix Inc.
    Inventors: Sun Ki CHO, Dae Han KWON
  • Publication number: 20190348418
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
  • Publication number: 20190318772
    Abstract: A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.
    Type: Application
    Filed: November 13, 2018
    Publication date: October 17, 2019
    Applicant: SK hynix Inc.
    Inventors: Bo Ram KIM, Dae Han KWON
  • Publication number: 20190312550
    Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Hae Kang JUNG, Yong Suk CHOI, Yong Bin KIM, Gyunam JEON, Dae-Han KWON, Joo Hwan CHO
  • Publication number: 20190287587
    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.
    Type: Application
    Filed: November 19, 2018
    Publication date: September 19, 2019
    Inventors: Dong Hyun KIM, Dae Han KWON, Kwan Su SHON, Soon Ku KANG, Jung Hyun SHIN, Doo Bock LEE, Yo Han JEONG, Eun Ji CHOI, Tae Jin HWANG
  • Patent number: 10411014
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
  • Publication number: 20190253055
    Abstract: A clock distribution circuit may include a data clock generation circuit configured to generate an internal clock signal using an external clock signal. The clock distribution circuit may be configured to receive the internal clock signal through a first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through a second circuit coupled to a global line. A first bias voltage provided to the first circuit and the data clock generation circuit and a second bias voltage provided to the second circuit may be controlled independently of each other.
    Type: Application
    Filed: August 17, 2018
    Publication date: August 15, 2019
    Applicant: SK hynix Inc.
    Inventors: Soo Young JANG, Dae Han KWON, Geun Il LEE, Kyu Dong HWANG
  • Publication number: 20190252013
    Abstract: A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.
    Type: Application
    Filed: December 12, 2018
    Publication date: August 15, 2019
    Applicant: SK hynix Inc.
    Inventors: Kyu Dong HWANG, Dae Han KWON
  • Patent number: 10367544
    Abstract: Methods and apparatuses are provided for searching for a cell by a communication processor (CP) of a wireless terminal having a plurality of antennas. One of the plurality of antennas is selected based on whether a secondary antenna is in a driving state and whether a finger of a rake receiver has been allocated. The plurality of antennas includes a primary antenna and the secondary antenna. A cell search is performed through the selected one of the plurality of antennas.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Dae-Cheol Kwon, Jong-Han Kim, Jae-Hyung Lee
  • Patent number: 10298733
    Abstract: A method by an electronic device may include detecting a bio-signal related to a user of the electronic device from at least one biometric sensor of the electronic device, and switching a mode or controlling a volume of a communication session between the electronic device and another electronic device based on at least part of the bio-signal. Other embodiments are also possible.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Ung Jeong, Hyou-Joo Kwon, Tae-Han Lee, Won-Suk Choi
  • Patent number: 10282167
    Abstract: A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. The buffer may include a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Dae Han Kwon
  • Patent number: 10256823
    Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Dae-Han Kwon, Shin-Deok Kang