Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A receiving device may include a buffer, a summer circuit, a first delay cell, and a second delay cell. The buffer may receive an external signal. The summer circuit may sum an output of the buffer, a first feedback signal, and a second feedback signal. The first delay cell may generate the first feedback signal by delaying an output of the summer circuit. The second delay cell may generate the second feedback signal by delaying the first feedback signal. The delay amounts of the first and second delay cells may be set based on a delay control voltage.

Abstract: An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.

Abstract: An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.

Abstract: A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. The buffer may include a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals.

Abstract: A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A duty cycle detection circuit includes a reset unit suitable for resetting a first capacitor and a second capacitor based on a reset signal, a first charging/discharging unit suitable for charging the first capacitor while a clock is in a first level and discharging the first capacitor while the clock is in a second level, a second charging/discharging unit suitable for charging the second capacitor while the clock is in the second level and discharging the second capacitor while the clock is in the first level, and a differential amplifier suitable for amplifying a voltage difference between the first capacitor and the second capacitor based on an amplification enable signal and generating a detection signal as a result of the amplification.

Abstract: A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.

Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.

Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.

Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.

Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

Abstract: A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.