Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

Abstract: A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.

Abstract: An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.

Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract: A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.

Abstract: A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

Abstract: A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.

Abstract: A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

Abstract: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

Abstract: There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

Abstract: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

Abstract: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

Abstract: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

Abstract: A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode.

Abstract: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

Abstract: A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

Abstract: A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

Abstract: A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.